si4455_defs.h

/*!
 * Silicon Laboratories Confidential
 * Copyright 2011 Silicon Laboratories, Inc.
 *
 * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT!
 */

#ifndef _SI4455_DEFS_H_
#define _SI4455_DEFS_H_


/* This section contains command map declarations */
struct si4455_reply_GENERIC_map {
    U8  REPLY1;
    U8  REPLY2;
    U8  REPLY3;
    U8  REPLY4;
    U8  REPLY5;
    U8  REPLY6;
    U8  REPLY7;
    U8  REPLY8;
    U8  REPLY9;
    U8  REPLY10;
    U8  REPLY11;
    U8  REPLY12;
    U8  REPLY13;
    U8  REPLY14;
    U8  REPLY15;
    U8  REPLY16;
};

struct si4455_reply_PART_INFO_map {
    U8  CHIPREV;
    UU16 PART;
    U8  PBUILD;
    UU16 ID;
    U8  CUSTOMER;
    U8  ROMID;
    U8  BOND;
};

struct si4455_reply_TEST_DATA_map {
    U8  TEST0;
    U8  TEST1;
    U8  TEST2;
    U8  TEST3;
    U8  TEST4;
    U8  TEST5;
    U8  TEST6;
    U8  TEST7;
    U8  TEST8;
    U8  TEST9;
    U8  TESTA;
    U8  TESTB;
    U8  TESTC;
    U8  TESTD;
    U8  TESTE;
    U8  TESTF;
};

struct si4455_reply_FUNC_INFO_map {
    U8  REVEXT;
    U8  REVBRANCH;
    U8  REVINT;
    UU16 PATCH;
    U8  FUNC;
    U8  SVNFLAGS;
    UU32 SVNREV;
};

struct si4455_reply_GET_PROPERTY_map {
    U8  DATA0;
    U8  DATA1;
    U8  DATA2;
    U8  DATA3;
    U8  DATA4;
    U8  DATA5;
    U8  DATA6;
    U8  DATA7;
    U8  DATA8;
    U8  DATA9;
    U8  DATA10;
    U8  DATA11;
    U8  DATA12;
    U8  DATA13;
    U8  DATA14;
    U8  DATA15;
};

struct si4455_reply_GPIO_PIN_CFG_map {
    U8  GPIO0;
    U8  GPIO1;
    U8  GPIO2;
    U8  GPIO3;
    U8  NIRQ;
    U8  SDO;
    U8  GEN_CONFIG;
};

struct si4455_reply_FIFO_INFO_map {
    U8  RX_FIFO_COUNT;
    U8  TX_FIFO_SPACE;
};

struct si4455_reply_EZCONFIG_CHECK_map {
    U8  RESULT;
};

struct si4455_reply_GET_INT_STATUS_map {
    U8  INT_PEND;
    U8  INT_STATUS;
    U8  PH_PEND;
    U8  PH_STATUS;
    U8  MODEM_PEND;
    U8  MODEM_STATUS;
    U8  CHIP_PEND;
    U8  CHIP_STATUS;
};

struct si4455_reply_GET_PH_STATUS_map {
    U8  PH_PEND;
    U8  PH_STATUS;
};

struct si4455_reply_GET_MODEM_STATUS_map {
    U8  MODEM_PEND;
    U8  MODEM_STATUS;
    U8  CURR_RSSI;
    U8  LATCH_RSSI;
    U8  ANT1_RSSI;
    U8  ANT2_RSSI;
    UU16 AFC_FREQ_OFFSET;
};

struct si4455_reply_GET_CHIP_STATUS_map {
    U8  CHIP_PEND;
    U8  CHIP_STATUS;
    U8  CMD_ERR_STATUS;
};

struct si4455_reply_REQUEST_DEVICE_STATE_map {
    U8  CURR_STATE;
    U8  CURRENT_CHANNEL;
};

struct si4455_reply_READ_CMD_BUFF_map {
    U8  CMD_BUFF0;
    U8  CMD_BUFF1;
    U8  CMD_BUFF2;
    U8  CMD_BUFF3;
    U8  CMD_BUFF4;
    U8  CMD_BUFF5;
    U8  CMD_BUFF6;
    U8  CMD_BUFF7;
    U8  CMD_BUFF8;
    U8  CMD_BUFF9;
    U8  CMD_BUFF10;
    U8  CMD_BUFF11;
    U8  CMD_BUFF12;
    U8  CMD_BUFF13;
    U8  CMD_BUFF14;
    U8  CMD_BUFF15;
};

struct si4455_reply_FRR_A_READ_map {
    U8  FRR_A_VALUE;
    U8  FRR_B_VALUE;
    U8  FRR_C_VALUE;
    U8  FRR_D_VALUE;
};

struct si4455_reply_FRR_B_READ_map {
    U8  FRR_B_VALUE;
    U8  FRR_C_VALUE;
    U8  FRR_D_VALUE;
    U8  FRR_A_VALUE;
};

struct si4455_reply_FRR_C_READ_map {
    U8  FRR_C_VALUE;
    U8  FRR_D_VALUE;
    U8  FRR_A_VALUE;
    U8  FRR_B_VALUE;
};

struct si4455_reply_FRR_D_READ_map {
    U8  FRR_D_VALUE;
    U8  FRR_A_VALUE;
    U8  FRR_B_VALUE;
    U8  FRR_C_VALUE;
};

struct si4455_reply_GET_ADC_READING_map {
    UU16 GPIO_ADC;
    UU16 BATTERY_ADC;
    UU16 TEMP_ADC;
    U8  TEMP_SLOPE;
    U8  TEMP_INTERCEPT;
};


/* The union that stores the reply written back to the host registers */
union si4455_cmd_reply_union {
    U8                                                                     RAW[16];
    struct si4455_reply_GENERIC_map                                        GENERIC;
    struct si4455_reply_PART_INFO_map                                      PART_INFO;
    struct si4455_reply_TEST_DATA_map                                      TEST_DATA;
    struct si4455_reply_FUNC_INFO_map                                      FUNC_INFO;
    struct si4455_reply_GET_PROPERTY_map                                   GET_PROPERTY;
    struct si4455_reply_GPIO_PIN_CFG_map                                   GPIO_PIN_CFG;
    struct si4455_reply_FIFO_INFO_map                                      FIFO_INFO;
    struct si4455_reply_EZCONFIG_CHECK_map                                 EZCONFIG_CHECK;
    struct si4455_reply_GET_INT_STATUS_map                                 GET_INT_STATUS;
    struct si4455_reply_GET_PH_STATUS_map                                  GET_PH_STATUS;
    struct si4455_reply_GET_MODEM_STATUS_map                               GET_MODEM_STATUS;
    struct si4455_reply_GET_CHIP_STATUS_map                                GET_CHIP_STATUS;
    struct si4455_reply_REQUEST_DEVICE_STATE_map                           REQUEST_DEVICE_STATE;
    struct si4455_reply_READ_CMD_BUFF_map                                  READ_CMD_BUFF;
    struct si4455_reply_FRR_A_READ_map                                     FRR_A_READ;
    struct si4455_reply_FRR_B_READ_map                                     FRR_B_READ;
    struct si4455_reply_FRR_C_READ_map                                     FRR_C_READ;
    struct si4455_reply_FRR_D_READ_map                                     FRR_D_READ;
    struct si4455_reply_GET_ADC_READING_map                                GET_ADC_READING;
};


#define SI4455_CMD_ID_NOP                                                      0x00
//NOP ARGS
#define SI4455_CMD_ARG_COUNT_NOP                                               1
//NOP REPLY
#define SI4455_CMD_REPLY_COUNT_NOP                                             0

#define SI4455_CMD_ID_PART_INFO                                                0x01
//PART_INFO ARGS
#define SI4455_CMD_ARG_COUNT_PART_INFO                                         1
//PART_INFO REPLY
#define SI4455_CMD_REPLY_COUNT_PART_INFO                                       9
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_TYPE u8
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_SIZE 8
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_MASK 0xFF
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_MSB  7
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_LSB  0
    #define SI4455_CMD_PART_INFO_REP_CHIPREV_INDEX 1
    #define SI4455_CMD_PART_INFO_REP_PART_TYPE u16
    #define SI4455_CMD_PART_INFO_REP_PART_SIZE 16
    #define SI4455_CMD_PART_INFO_REP_PART_MASK 0xFFFF
    #define SI4455_CMD_PART_INFO_REP_PART_MSB  15
    #define SI4455_CMD_PART_INFO_REP_PART_LSB  0
    #define SI4455_CMD_PART_INFO_REP_PART_INDEX 2
    #define SI4455_CMD_PART_INFO_REP_PBUILD_TYPE u8
    #define SI4455_CMD_PART_INFO_REP_PBUILD_SIZE 8
    #define SI4455_CMD_PART_INFO_REP_PBUILD_MASK 0xFF
    #define SI4455_CMD_PART_INFO_REP_PBUILD_MSB  7
    #define SI4455_CMD_PART_INFO_REP_PBUILD_LSB  0
    #define SI4455_CMD_PART_INFO_REP_PBUILD_INDEX 4
    #define SI4455_CMD_PART_INFO_REP_ID_TYPE u16
    #define SI4455_CMD_PART_INFO_REP_ID_SIZE 16
    #define SI4455_CMD_PART_INFO_REP_ID_MASK 0xFFFF
    #define SI4455_CMD_PART_INFO_REP_ID_MSB  15
    #define SI4455_CMD_PART_INFO_REP_ID_LSB  0
    #define SI4455_CMD_PART_INFO_REP_ID_INDEX 5
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_TYPE u8
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_SIZE 8
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_MASK 0xFF
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_MSB  7
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_LSB  0
    #define SI4455_CMD_PART_INFO_REP_CUSTOMER_INDEX 7
    #define SI4455_CMD_PART_INFO_REP_ROMID_TYPE u8
    #define SI4455_CMD_PART_INFO_REP_ROMID_SIZE 8
    #define SI4455_CMD_PART_INFO_REP_ROMID_MASK 0xFF
    #define SI4455_CMD_PART_INFO_REP_ROMID_MSB  7
    #define SI4455_CMD_PART_INFO_REP_ROMID_LSB  0
    #define SI4455_CMD_PART_INFO_REP_ROMID_INDEX 8
    #define SI4455_CMD_PART_INFO_REP_BOND_TYPE u8
    #define SI4455_CMD_PART_INFO_REP_BOND_SIZE 8
    #define SI4455_CMD_PART_INFO_REP_BOND_MASK 0xFF
    #define SI4455_CMD_PART_INFO_REP_BOND_MSB  7
    #define SI4455_CMD_PART_INFO_REP_BOND_LSB  0
    #define SI4455_CMD_PART_INFO_REP_BOND_INDEX 9

#define SI4455_CMD_ID_POWER_UP                                                 0x02
//POWER_UP ARGS
#define SI4455_CMD_ARG_COUNT_POWER_UP                                          7
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_TYPE bitfield
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_SIZE 8
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_MASK 0xFF
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_MSB  7
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_LSB  0
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_INDEX 1
    #define SI4455_CMD_POWER_UP_ARG_BOOT_OPTIONS_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_POWER_UP_ARG_PATCH_TYPE bitfield
    #define SI4455_CMD_POWER_UP_ARG_PATCH_SIZE 1
    #define SI4455_CMD_POWER_UP_ARG_PATCH_MASK 0x80
    #define SI4455_CMD_POWER_UP_ARG_PATCH_BIT  0x80
    #define SI4455_CMD_POWER_UP_ARG_PATCH_MSB  7
    #define SI4455_CMD_POWER_UP_ARG_PATCH_LSB  7
    #define SI4455_CMD_POWER_UP_ARG_PATCH_INDEX 1
    #define SI4455_CMD_POWER_UP_ARG_PATCH_is_true (cmd.arg.RAW[1]&0x80)
    #define SI4455_CMD_POWER_UP_ARG_PATCH_value (((cmd.arg.RAW[1]&0x80))>>7)
    #define SI4455_CMD_POWER_UP_ARG_FUNC_TYPE bitfield
    #define SI4455_CMD_POWER_UP_ARG_FUNC_SIZE 6
    #define SI4455_CMD_POWER_UP_ARG_FUNC_MASK 0x3F
    #define SI4455_CMD_POWER_UP_ARG_FUNC_MSB  5
    #define SI4455_CMD_POWER_UP_ARG_FUNC_LSB  0
    #define SI4455_CMD_POWER_UP_ARG_FUNC_INDEX 1
    #define SI4455_CMD_POWER_UP_ARG_FUNC_value (((cmd.arg.RAW[1]&0x3F)))
    #define SI4455_CMD_POWER_UP_ARG_FUNC_ENUM_BOOT 0
    #define SI4455_CMD_POWER_UP_ARG_FUNC_ENUM_MAIN 1
    #define SI4455_CMD_POWER_UP_ARG_FUNC_ENUM_LOADED 63
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_TYPE bitfield
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_SIZE 8
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_MASK 0xFF
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_MSB  7
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_LSB  0
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_INDEX 2
    #define SI4455_CMD_POWER_UP_ARG_XTAL_OPTIONS_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_POWER_UP_ARG_TCXO_TYPE bitfield
    #define SI4455_CMD_POWER_UP_ARG_TCXO_SIZE 1
    #define SI4455_CMD_POWER_UP_ARG_TCXO_MASK 0x01
    #define SI4455_CMD_POWER_UP_ARG_TCXO_BIT  0x01
    #define SI4455_CMD_POWER_UP_ARG_TCXO_MSB  0
    #define SI4455_CMD_POWER_UP_ARG_TCXO_LSB  0
    #define SI4455_CMD_POWER_UP_ARG_TCXO_INDEX 2
    #define SI4455_CMD_POWER_UP_ARG_TCXO_is_true (cmd.arg.RAW[2]&0x1)
    #define SI4455_CMD_POWER_UP_ARG_TCXO_value (((cmd.arg.RAW[2]&0x1)))
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_TYPE u32
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_SIZE 32
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_MASK 0xFFFFFFFF
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_MSB  31
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_LSB  0
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_INDEX 3
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_value (((cmd.arg.RAW_u32[0])))
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_MIN 25000000
    #define SI4455_CMD_POWER_UP_ARG_XO_FREQ_MAX 32000000
//POWER_UP REPLY
#define SI4455_CMD_REPLY_COUNT_POWER_UP                                        0

#define SI4455_CMD_ID_TEST_DATA                                                0x09
//TEST_DATA ARGS
#define SI4455_CMD_ARG_COUNT_TEST_DATA                                         2
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_TYPE u8
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_SIZE 8
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_MSB  7
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_LSB  0
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_INDEX 1
    #define SI4455_CMD_TEST_DATA_ARG_OFFSET_value (((cmd.arg.RAW[1])))
//TEST_DATA REPLY
#define SI4455_CMD_REPLY_COUNT_TEST_DATA                                       16
    #define SI4455_CMD_TEST_DATA_REP_TEST0_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST0_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST0_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST0_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST0_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST0_INDEX 1
    #define SI4455_CMD_TEST_DATA_REP_TEST1_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST1_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST1_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST1_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST1_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST1_INDEX 2
    #define SI4455_CMD_TEST_DATA_REP_TEST2_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST2_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST2_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST2_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST2_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST2_INDEX 3
    #define SI4455_CMD_TEST_DATA_REP_TEST3_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST3_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST3_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST3_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST3_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST3_INDEX 4
    #define SI4455_CMD_TEST_DATA_REP_TEST4_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST4_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST4_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST4_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST4_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST4_INDEX 5
    #define SI4455_CMD_TEST_DATA_REP_TEST5_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST5_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST5_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST5_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST5_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST5_INDEX 6
    #define SI4455_CMD_TEST_DATA_REP_TEST6_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST6_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST6_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST6_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST6_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST6_INDEX 7
    #define SI4455_CMD_TEST_DATA_REP_TEST7_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST7_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST7_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST7_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST7_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST7_INDEX 8
    #define SI4455_CMD_TEST_DATA_REP_TEST8_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST8_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST8_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST8_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST8_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST8_INDEX 9
    #define SI4455_CMD_TEST_DATA_REP_TEST9_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TEST9_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TEST9_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TEST9_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TEST9_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TEST9_INDEX 10
    #define SI4455_CMD_TEST_DATA_REP_TESTA_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTA_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTA_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTA_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTA_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTA_INDEX 11
    #define SI4455_CMD_TEST_DATA_REP_TESTB_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTB_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTB_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTB_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTB_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTB_INDEX 12
    #define SI4455_CMD_TEST_DATA_REP_TESTC_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTC_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTC_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTC_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTC_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTC_INDEX 13
    #define SI4455_CMD_TEST_DATA_REP_TESTD_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTD_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTD_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTD_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTD_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTD_INDEX 14
    #define SI4455_CMD_TEST_DATA_REP_TESTE_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTE_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTE_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTE_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTE_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTE_INDEX 15
    #define SI4455_CMD_TEST_DATA_REP_TESTF_TYPE u8
    #define SI4455_CMD_TEST_DATA_REP_TESTF_SIZE 8
    #define SI4455_CMD_TEST_DATA_REP_TESTF_MASK 0xFF
    #define SI4455_CMD_TEST_DATA_REP_TESTF_MSB  7
    #define SI4455_CMD_TEST_DATA_REP_TESTF_LSB  0
    #define SI4455_CMD_TEST_DATA_REP_TESTF_INDEX 16

#define SI4455_CMD_ID_FUNC_INFO                                                0x10
//FUNC_INFO ARGS
#define SI4455_CMD_ARG_COUNT_FUNC_INFO                                         1
//FUNC_INFO REPLY
#define SI4455_CMD_REPLY_COUNT_FUNC_INFO                                       11
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_TYPE u8
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_SIZE 8
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_MASK 0xFF
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_MSB  7
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_INDEX 1
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_MIN 0
    #define SI4455_CMD_FUNC_INFO_REP_REVEXT_MAX 255
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_TYPE u8
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_SIZE 8
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_MASK 0xFF
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_MSB  7
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_INDEX 2
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_MIN 0
    #define SI4455_CMD_FUNC_INFO_REP_REVBRANCH_MAX 255
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_TYPE u8
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_SIZE 8
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_MASK 0xFF
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_MSB  7
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_INDEX 3
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_MIN 0
    #define SI4455_CMD_FUNC_INFO_REP_REVINT_MAX 255
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_TYPE u16
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_SIZE 16
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_MASK 0xFFFF
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_MSB  15
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_PATCH_INDEX 4
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_TYPE u8
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_SIZE 8
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_MASK 0xFF
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_MSB  7
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_INDEX 6
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_ENUM_BOOT 0
    #define SI4455_CMD_FUNC_INFO_REP_FUNC_ENUM_MAIN 1
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_TYPE bitfield
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_SIZE 8
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_MASK 0xFF
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_MSB  7
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_SVNFLAGS_INDEX 7
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_TYPE bitfield
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_SIZE 2
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_MASK 0x30
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_MSB  5
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_LSB  4
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_INDEX 7
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_ENUM_TAG 0
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_ENUM_BRANCH 1
    #define SI4455_CMD_FUNC_INFO_REP_LOCATION_ENUM_TRUNK 2
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_TYPE bitfield
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_SIZE 1
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_MASK 0x02
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_BIT  0x02
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_MSB  1
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_LSB  1
    #define SI4455_CMD_FUNC_INFO_REP_MIXEDREV_INDEX 7
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_TYPE bitfield
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_SIZE 1
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_MASK 0x01
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_BIT  0x01
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_MSB  0
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_LOCALMOD_INDEX 7
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_TYPE u32
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_SIZE 32
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_MASK 0xFFFFFFFF
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_MSB  31
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_LSB  0
    #define SI4455_CMD_FUNC_INFO_REP_SVNREV_INDEX 8

#define SI4455_CMD_ID_SET_PROPERTY                                             0x11
//SET_PROPERTY ARGS
#define SI4455_CMD_ARG_COUNT_SET_PROPERTY                                      16
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_INDEX 1
    #define SI4455_CMD_SET_PROPERTY_ARG_GROUP_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_INDEX 2
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_MIN 1
    #define SI4455_CMD_SET_PROPERTY_ARG_NUM_PROPS_MAX 12
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_INDEX 3
    #define SI4455_CMD_SET_PROPERTY_ARG_START_PROP_value (((cmd.arg.RAW[3])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_INDEX 4
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA0_value (((cmd.arg.RAW[4])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_INDEX 5
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA1_value (((cmd.arg.RAW[5])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_INDEX 6
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA2_value (((cmd.arg.RAW[6])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_INDEX 7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA3_value (((cmd.arg.RAW[7])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_INDEX 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA4_value (((cmd.arg.RAW[8])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_INDEX 9
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA5_value (((cmd.arg.RAW[9])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_INDEX 10
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA6_value (((cmd.arg.RAW[10])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_INDEX 11
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA7_value (((cmd.arg.RAW[11])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_INDEX 12
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA8_value (((cmd.arg.RAW[12])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_INDEX 13
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA9_value (((cmd.arg.RAW[13])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_INDEX 14
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA10_value (((cmd.arg.RAW[14])))
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_TYPE u8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_SIZE 8
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_MASK 0xFF
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_MSB  7
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_LSB  0
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_INDEX 15
    #define SI4455_CMD_SET_PROPERTY_ARG_DATA11_value (((cmd.arg.RAW[15])))
//SET_PROPERTY REPLY
#define SI4455_CMD_REPLY_COUNT_SET_PROPERTY                                    0

#define SI4455_CMD_ID_GET_PROPERTY                                             0x12
//GET_PROPERTY ARGS
#define SI4455_CMD_ARG_COUNT_GET_PROPERTY                                      4
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_MSB  7
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_LSB  0
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_INDEX 1
    #define SI4455_CMD_GET_PROPERTY_ARG_GROUP_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_MSB  7
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_LSB  0
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_INDEX 2
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_MIN 1
    #define SI4455_CMD_GET_PROPERTY_ARG_NUM_PROPS_MAX 16
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_MSB  7
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_LSB  0
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_INDEX 3
    #define SI4455_CMD_GET_PROPERTY_ARG_START_PROP_value (((cmd.arg.RAW[3])))
//GET_PROPERTY REPLY
#define SI4455_CMD_REPLY_COUNT_GET_PROPERTY                                    16
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA0_INDEX 1
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA1_INDEX 2
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA2_INDEX 3
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA3_INDEX 4
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA4_INDEX 5
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA5_INDEX 6
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA6_INDEX 7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA7_INDEX 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA8_INDEX 9
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA9_INDEX 10
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA10_INDEX 11
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA11_INDEX 12
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA12_INDEX 13
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA13_INDEX 14
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA14_INDEX 15
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_TYPE u8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_SIZE 8
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_MASK 0xFF
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_MSB  7
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_LSB  0
    #define SI4455_CMD_GET_PROPERTY_REP_DATA15_INDEX 16

#define SI4455_CMD_ID_GPIO_PIN_CFG                                             0x13
//GPIO_PIN_CFG ARGS
#define SI4455_CMD_ARG_COUNT_GPIO_PIN_CFG                                      8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_is_true (cmd.arg.RAW[1]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_value (((cmd.arg.RAW[1]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_value (((cmd.arg.RAW[1]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_is_true (cmd.arg.RAW[2]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_value (((cmd.arg.RAW[2]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_value (((cmd.arg.RAW[2]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_value (((cmd.arg.RAW[3])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_is_true (cmd.arg.RAW[3]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_value (((cmd.arg.RAW[3]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_value (((cmd.arg.RAW[3]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_value (((cmd.arg.RAW[4])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_is_true (cmd.arg.RAW[4]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_value (((cmd.arg.RAW[4]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_value (((cmd.arg.RAW[4]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_value (((cmd.arg.RAW[5])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_is_true (cmd.arg.RAW[5]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_value (((cmd.arg.RAW[5]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_value (((cmd.arg.RAW[5]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_NIRQ 39
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_value (((cmd.arg.RAW[6])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_MASK 0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_BIT  0x40
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_LSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_is_true (cmd.arg.RAW[6]&0x40)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_value (((cmd.arg.RAW[6]&0x40))>>6)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_ENUM_PULL_DIS 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_ENUM_PULL_EN 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_value (((cmd.arg.RAW[6]&0x3F)))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_INDEX 7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_value (((cmd.arg.RAW[7])))
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_SIZE 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_MASK 0x60
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_LSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_INDEX 7
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_value (((cmd.arg.RAW[7]&0x60))>>5)
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_HIGH 0
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_MED_HIGH 1
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_MED_LOW 2
    #define SI4455_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_LOW 3
//GPIO_PIN_CFG REPLY
#define SI4455_CMD_REPLY_COUNT_GPIO_PIN_CFG                                    7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_INDEX 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_INDEX 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_INDEX 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_INDEX 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_STATE 32
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_STATE 33
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_FIFO_FULL 34
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_FIFO_EMPTY 35
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQ_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_INDEX 5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_NIRQ 39
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDO_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_SIZE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_MASK 0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_BIT  0x80
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_LSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOSTATE_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_SIZE 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_MASK 0x3F
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_MSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_INDEX 6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DONOTHING 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_TRISTATE 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DRIVE0 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DRIVE1 3
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_INPUT 4
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_SDO 11
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_POR 12
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_TX_DATA_CLK 16
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_DATA_CLK 17
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_TX_DATA 19
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_DATA 20
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_RAW_DATA 21
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_VALID_PREAMBLE 24
    #define SI4455_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_SYNC_WORD_DETECT 26
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_SIZE 8
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_MASK 0xFF
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_MSB  7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_LSB  0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_INDEX 7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_TYPE bitfield
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_SIZE 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_MASK 0x60
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_MSB  6
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_LSB  5
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_INDEX 7
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_HIGH 0
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_MED_HIGH 1
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_MED_LOW 2
    #define SI4455_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_LOW 3

#define SI4455_CMD_ID_GET_ADC_READING                                          0x14
//GET_ADC_READING ARGS
#define SI4455_CMD_ARG_COUNT_GET_ADC_READING                                   3
//GET_ADC_READING REPLY
#define SI4455_CMD_REPLY_COUNT_GET_ADC_READING                                 8

#define SI4455_CMD_ID_FIFO_INFO                                                0x15
//FIFO_INFO ARGS
#define SI4455_CMD_ARG_COUNT_FIFO_INFO                                         2
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_TYPE bitfield
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_SIZE 8
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_MASK 0xFF
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_MSB  7
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_LSB  0
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_INDEX 1
    #define SI4455_CMD_FIFO_INFO_ARG_FIFO_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_FIFO_INFO_ARG_RX_TYPE bitfield
    #define SI4455_CMD_FIFO_INFO_ARG_RX_SIZE 1
    #define SI4455_CMD_FIFO_INFO_ARG_RX_MASK 0x02
    #define SI4455_CMD_FIFO_INFO_ARG_RX_BIT  0x02
    #define SI4455_CMD_FIFO_INFO_ARG_RX_MSB  1
    #define SI4455_CMD_FIFO_INFO_ARG_RX_LSB  1
    #define SI4455_CMD_FIFO_INFO_ARG_RX_INDEX 1
    #define SI4455_CMD_FIFO_INFO_ARG_RX_is_true (cmd.arg.RAW[1]&0x2)
    #define SI4455_CMD_FIFO_INFO_ARG_RX_value (((cmd.arg.RAW[1]&0x2))>>1)
    #define SI4455_CMD_FIFO_INFO_ARG_RX_ENUM_FALSE 0
    #define SI4455_CMD_FIFO_INFO_ARG_RX_ENUM_TRUE 1
    #define SI4455_CMD_FIFO_INFO_ARG_TX_TYPE bitfield
    #define SI4455_CMD_FIFO_INFO_ARG_TX_SIZE 1
    #define SI4455_CMD_FIFO_INFO_ARG_TX_MASK 0x01
    #define SI4455_CMD_FIFO_INFO_ARG_TX_BIT  0x01
    #define SI4455_CMD_FIFO_INFO_ARG_TX_MSB  0
    #define SI4455_CMD_FIFO_INFO_ARG_TX_LSB  0
    #define SI4455_CMD_FIFO_INFO_ARG_TX_INDEX 1
    #define SI4455_CMD_FIFO_INFO_ARG_TX_is_true (cmd.arg.RAW[1]&0x1)
    #define SI4455_CMD_FIFO_INFO_ARG_TX_value (((cmd.arg.RAW[1]&0x1)))
    #define SI4455_CMD_FIFO_INFO_ARG_TX_ENUM_FALSE 0
    #define SI4455_CMD_FIFO_INFO_ARG_TX_ENUM_TRUE 1
//FIFO_INFO REPLY
#define SI4455_CMD_REPLY_COUNT_FIFO_INFO                                       2
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_TYPE u8
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_SIZE 8
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_MASK 0xFF
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_MSB  7
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_LSB  0
    #define SI4455_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_INDEX 1
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_TYPE u8
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_SIZE 8
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_MASK 0xFF
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_MSB  7
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_LSB  0
    #define SI4455_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_INDEX 2

#define SI4455_CMD_ID_EZCONFIG_CHECK                                           0x19
//EZCONFIG_CHECK ARGS
#define SI4455_CMD_ARG_COUNT_EZCONFIG_CHECK                                    3
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_TYPE u16
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_SIZE 16
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_MASK 0xFFFF
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_MSB  15
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_LSB  0
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_INDEX 1
    #define SI4455_CMD_EZCONFIG_CHECK_ARG_CHECKSUM_value (((cmd.arg.RAW_u16[0])))
//EZCONFIG_CHECK REPLY
#define SI4455_CMD_REPLY_COUNT_EZCONFIG_CHECK                                  1
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_TYPE u8
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_SIZE 8
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_MASK 0xFF
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_MSB  7
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_LSB  0
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_INDEX 1
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_ENUM_VALID 0
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_ENUM_BAD_CHECKSUM 1
    #define SI4455_CMD_EZCONFIG_CHECK_REP_RESULT_ENUM_INVALID_STATE 2

#define SI4455_CMD_ID_GET_INT_STATUS                                           0x20
//GET_INT_STATUS ARGS
#define SI4455_CMD_ARG_COUNT_GET_INT_STATUS                                    4
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_is_true (cmd.arg.RAW[1]&0x20)
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_value (((cmd.arg.RAW[1]&0x20))>>5)
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_is_true (cmd.arg.RAW[1]&0x10)
    #define SI4455_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_value (((cmd.arg.RAW[1]&0x10))>>4)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_is_true (cmd.arg.RAW[1]&0x8)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_value (((cmd.arg.RAW[1]&0x8))>>3)
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_is_true (cmd.arg.RAW[1]&0x2)
    #define SI4455_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_value (((cmd.arg.RAW[1]&0x2))>>1)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_is_true (cmd.arg.RAW[1]&0x1)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_value (((cmd.arg.RAW[1]&0x1)))
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x40)
    #define SI4455_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x40))>>6)
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_is_true (cmd.arg.RAW[2]&0x20)
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_value (((cmd.arg.RAW[2]&0x20))>>5)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_is_true (cmd.arg.RAW[2]&0x10)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_value (((cmd.arg.RAW[2]&0x10))>>4)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_is_true (cmd.arg.RAW[2]&0x8)
    #define SI4455_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_value (((cmd.arg.RAW[2]&0x8))>>3)
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_is_true (cmd.arg.RAW[2]&0x4)
    #define SI4455_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_value (((cmd.arg.RAW[2]&0x4))>>2)
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x2)
    #define SI4455_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x2))>>1)
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x1)
    #define SI4455_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x1)))
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_value (((cmd.arg.RAW[3])))
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_is_true (cmd.arg.RAW[3]&0x40)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_value (((cmd.arg.RAW[3]&0x40))>>6)
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_is_true (cmd.arg.RAW[3]&0x20)
    #define SI4455_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_value (((cmd.arg.RAW[3]&0x20))>>5)
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_is_true (cmd.arg.RAW[3]&0x10)
    #define SI4455_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_value (((cmd.arg.RAW[3]&0x10))>>4)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_is_true (cmd.arg.RAW[3]&0x8)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_value (((cmd.arg.RAW[3]&0x8))>>3)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_is_true (cmd.arg.RAW[3]&0x4)
    #define SI4455_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_value (((cmd.arg.RAW[3]&0x4))>>2)
//GET_INT_STATUS REPLY
#define SI4455_CMD_REPLY_COUNT_GET_INT_STATUS                                  8
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_PEND_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_INDEX 1
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_INT_STATUS_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_INDEX 2
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_INDEX 3
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_PH_STATUS_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_SENT_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_PACKET_RX_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CRC_ERROR_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_INDEX 4
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_INDEX 5
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_MODEM_STATUS_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_SYNC_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_JUMP_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_RSSI_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_MASK 0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_BIT  0x02
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_MSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_LSB  1
    #define SI4455_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_MASK 0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_BIT  0x01
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_MSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_SYNC_DETECT_INDEX 6
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_INDEX 7
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_SIZE 8
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_MSB  7
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_LSB  0
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_STATUS_INDEX 8
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_MASK 0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_BIT  0x40
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_MSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_LSB  6
    #define SI4455_CMD_GET_INT_STATUS_REP_CAL_INDEX 8
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MASK 0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_BIT  0x20
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_LSB  5
    #define SI4455_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_INDEX 8
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_MASK 0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_BIT  0x10
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_MSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_LSB  4
    #define SI4455_CMD_GET_INT_STATUS_REP_STATE_CHANGE_INDEX 8
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_MASK 0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_BIT  0x08
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_MSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_LSB  3
    #define SI4455_CMD_GET_INT_STATUS_REP_CMD_ERROR_INDEX 8
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_TYPE bitfield
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_SIZE 1
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_MASK 0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_BIT  0x04
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_MSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_LSB  2
    #define SI4455_CMD_GET_INT_STATUS_REP_CHIP_READY_INDEX 8


//GET_CHIP_STATUS REPLY
#define SI4455_CMD_REPLY_COUNT_GET_CHIP_STATUS                                 3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_SIZE 8
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_MASK 0xFF
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_MSB  7
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_LSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_MASK 0x40
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_BIT  0x40
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_MSB  6
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_LSB  6
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MASK 0x20
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_BIT  0x20
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MSB  5
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_LSB  5
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_MASK 0x10
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_BIT  0x10
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_MSB  4
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_LSB  4
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_MASK 0x08
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_BIT  0x08
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_MSB  3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_LSB  3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_MASK 0x04
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_BIT  0x04
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_MSB  2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_LSB  2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_MASK 0x02
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_BIT  0x02
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_MSB  1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_LSB  1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_MASK 0x01
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_BIT  0x01
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_MSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_LSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_PEND_INDEX 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_SIZE 8
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_MSB  7
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_LSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_MASK 0x40
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_BIT  0x40
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_MSB  6
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_LSB  6
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CAL_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MASK 0x20
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_BIT  0x20
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MSB  5
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_LSB  5
    #define SI4455_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_MASK 0x10
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_BIT  0x10
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_MSB  4
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_LSB  4
    #define SI4455_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_MASK 0x08
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_BIT  0x08
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_MSB  3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_LSB  3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_MASK 0x04
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_BIT  0x04
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_MSB  2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_LSB  2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CHIP_READY_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_MASK 0x02
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_BIT  0x02
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_MSB  1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_LSB  1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_LOW_BATT_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_TYPE bitfield
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_SIZE 1
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_MASK 0x01
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_BIT  0x01
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_MSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_LSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_WUT_INDEX 2
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_TYPE u8
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_SIZE 8
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_MASK 0xFF
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_MSB  7
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_LSB  0
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_INDEX 3
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_NONE 0x00
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_COMMAND 0x10
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_ARG 0x11
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_COMMAND_BUSY 0x12
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_NVM 0x20
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_PATCH 0x30
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_BOOTMODE 0x31
    #define SI4455_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_PROPERTY 0x40

#define SI4455_CMD_ID_GET_PH_STATUS                                           0x21
//GET_PH_STATUS ARGS
#define SI4455_CMD_ARG_COUNT_GET_PH_STATUS                                     2
//GET_PH_STATUS REPLY
#define SI4455_CMD_REPLY_COUNT_GET_PH_STATUS                                   2

#define SI4455_CMD_ID_GET_MODEM_STATUS                                         0x22
//GET_MODEM_STATUS ARGS
#define SI4455_CMD_ARG_COUNT_GET_MODEM_STATUS                                  2
//GET_MODEM_STATUS REPLY
#define SI4455_CMD_REPLY_COUNT_GET_MODEM_STATUS                                8

#define SI4455_CMD_ID_GET_CHIP_STATUS                                          0x23
//GET_CHIP_STATUS ARGS
#define SI4455_CMD_ARG_COUNT_GET_CHIP_STATUS                                   2
//GET_CHIP_STATUS REPLY
#define SI4455_CMD_REPLY_COUNT_GET_CHIP_STATUS                                 3

#define SI4455_CMD_ID_START_TX                                                 0x31
//START_TX ARGS
#define SI4455_CMD_ARG_COUNT_START_TX                                          5
    #define SI4455_CMD_START_TX_ARG_CHANNEL_TYPE u8
    #define SI4455_CMD_START_TX_ARG_CHANNEL_SIZE 8
    #define SI4455_CMD_START_TX_ARG_CHANNEL_MASK 0xFF
    #define SI4455_CMD_START_TX_ARG_CHANNEL_MSB  7
    #define SI4455_CMD_START_TX_ARG_CHANNEL_LSB  0
    #define SI4455_CMD_START_TX_ARG_CHANNEL_INDEX 1
    #define SI4455_CMD_START_TX_ARG_CHANNEL_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_START_TX_ARG_CHANNEL_MIN 0
    #define SI4455_CMD_START_TX_ARG_CHANNEL_MAX 255
    #define SI4455_CMD_START_TX_ARG_CONDITION_TYPE bitfield
    #define SI4455_CMD_START_TX_ARG_CONDITION_SIZE 8
    #define SI4455_CMD_START_TX_ARG_CONDITION_MASK 0xFF
    #define SI4455_CMD_START_TX_ARG_CONDITION_MSB  7
    #define SI4455_CMD_START_TX_ARG_CONDITION_LSB  0
    #define SI4455_CMD_START_TX_ARG_CONDITION_INDEX 2
    #define SI4455_CMD_START_TX_ARG_CONDITION_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_TYPE bitfield
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_SIZE 4
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_MASK 0xF0
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_MSB  7
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_LSB  4
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_INDEX 2
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_value (((cmd.arg.RAW[2]&0xF0))>>4)
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_READY 3
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_READY2 4
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_TX 7
    #define SI4455_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_RX 8
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_TYPE bitfield
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_SIZE 1
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_MASK 0x04
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_BIT  0x04
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_MSB  2
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_LSB  2
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_INDEX 2
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_is_true (cmd.arg.RAW[2]&0x4)
    #define SI4455_CMD_START_TX_ARG_RETRANSMIT_value (((cmd.arg.RAW[2]&0x4))>>2)
    #define SI4455_CMD_START_TX_ARG_START_TYPE bitfield
    #define SI4455_CMD_START_TX_ARG_START_SIZE 2
    #define SI4455_CMD_START_TX_ARG_START_MASK 0x03
    #define SI4455_CMD_START_TX_ARG_START_MSB  1
    #define SI4455_CMD_START_TX_ARG_START_LSB  0
    #define SI4455_CMD_START_TX_ARG_START_INDEX 2
    #define SI4455_CMD_START_TX_ARG_START_value (((cmd.arg.RAW[2]&0x3)))
    #define SI4455_CMD_START_TX_ARG_TX_LEN_TYPE u16
    #define SI4455_CMD_START_TX_ARG_TX_LEN_SIZE 16
    #define SI4455_CMD_START_TX_ARG_TX_LEN_MASK 0xFFFF
    #define SI4455_CMD_START_TX_ARG_TX_LEN_MSB  15
    #define SI4455_CMD_START_TX_ARG_TX_LEN_LSB  0
    #define SI4455_CMD_START_TX_ARG_TX_LEN_INDEX 3
    #define SI4455_CMD_START_TX_ARG_TX_LEN_value (((cmd.arg.RAW_u16[1])))
    #define SI4455_CMD_START_TX_ARG_TX_LEN_MIN 0
    #define SI4455_CMD_START_TX_ARG_TX_LEN_MAX 8191
//START_TX REPLY
#define SI4455_CMD_REPLY_COUNT_START_TX                                        0

#define SI4455_CMD_ID_START_RX                                                 0x32
//START_RX ARGS
#define SI4455_CMD_ARG_COUNT_START_RX                                          8
    #define SI4455_CMD_START_RX_ARG_CHANNEL_TYPE u8
    #define SI4455_CMD_START_RX_ARG_CHANNEL_SIZE 8
    #define SI4455_CMD_START_RX_ARG_CHANNEL_MASK 0xFF
    #define SI4455_CMD_START_RX_ARG_CHANNEL_MSB  7
    #define SI4455_CMD_START_RX_ARG_CHANNEL_LSB  0
    #define SI4455_CMD_START_RX_ARG_CHANNEL_INDEX 1
    #define SI4455_CMD_START_RX_ARG_CHANNEL_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_START_RX_ARG_CHANNEL_MIN 0
    #define SI4455_CMD_START_RX_ARG_CHANNEL_MAX 255
    #define SI4455_CMD_START_RX_ARG_CONDITION_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_CONDITION_SIZE 8
    #define SI4455_CMD_START_RX_ARG_CONDITION_MASK 0xFF
    #define SI4455_CMD_START_RX_ARG_CONDITION_MSB  7
    #define SI4455_CMD_START_RX_ARG_CONDITION_LSB  0
    #define SI4455_CMD_START_RX_ARG_CONDITION_INDEX 2
    #define SI4455_CMD_START_RX_ARG_CONDITION_value (((cmd.arg.RAW[2])))
    #define SI4455_CMD_START_RX_ARG_START_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_START_SIZE 1
    #define SI4455_CMD_START_RX_ARG_START_MASK 0x01
    #define SI4455_CMD_START_RX_ARG_START_BIT  0x01
    #define SI4455_CMD_START_RX_ARG_START_MSB  0
    #define SI4455_CMD_START_RX_ARG_START_LSB  0
    #define SI4455_CMD_START_RX_ARG_START_INDEX 2
    #define SI4455_CMD_START_RX_ARG_START_is_true (cmd.arg.RAW[2]&0x1)
    #define SI4455_CMD_START_RX_ARG_START_value (((cmd.arg.RAW[2]&0x1)))
    #define SI4455_CMD_START_RX_ARG_RX_LEN_TYPE u16
    #define SI4455_CMD_START_RX_ARG_RX_LEN_SIZE 16
    #define SI4455_CMD_START_RX_ARG_RX_LEN_MASK 0xFFFF
    #define SI4455_CMD_START_RX_ARG_RX_LEN_MSB  15
    #define SI4455_CMD_START_RX_ARG_RX_LEN_LSB  0
    #define SI4455_CMD_START_RX_ARG_RX_LEN_INDEX 3
    #define SI4455_CMD_START_RX_ARG_RX_LEN_value (((cmd.arg.RAW_u16[1])))
    #define SI4455_CMD_START_RX_ARG_RX_LEN_MIN 0
    #define SI4455_CMD_START_RX_ARG_RX_LEN_MAX 8191
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_SIZE 8
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_MASK 0xFF
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_MSB  7
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_LSB  0
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_INDEX 5
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE1_value (((cmd.arg.RAW[5])))
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_SIZE 4
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_MASK 0x0F
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_MSB  3
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_LSB  0
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_INDEX 5
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_value (((cmd.arg.RAW[5]&0xF)))
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_READY 3
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_READY2 4
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_TX 7
    #define SI4455_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_RX 8
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_SIZE 8
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_MASK 0xFF
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_MSB  7
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_LSB  0
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_INDEX 6
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE2_value (((cmd.arg.RAW[6])))
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_SIZE 4
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_MASK 0x0F
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_MSB  3
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_LSB  0
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_INDEX 6
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_value (((cmd.arg.RAW[6]&0xF)))
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_READY 3
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_READY2 4
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_TX 7
    #define SI4455_CMD_START_RX_ARG_RXVALID_STATE_ENUM_RX 8
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_SIZE 8
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_MASK 0xFF
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_MSB  7
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_LSB  0
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_INDEX 7
    #define SI4455_CMD_START_RX_ARG_NEXT_STATE3_value (((cmd.arg.RAW[7])))
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_TYPE bitfield
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_SIZE 4
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_MASK 0x0F
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_MSB  3
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_LSB  0
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_INDEX 7
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_value (((cmd.arg.RAW[7]&0xF)))
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_READY 3
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_READY2 4
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_TX 7
    #define SI4455_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_RX 8
//START_RX REPLY
#define SI4455_CMD_REPLY_COUNT_START_RX                                        0

#define SI4455_CMD_ID_REQUEST_DEVICE_STATE                                     0x33
//REQUEST_DEVICE_STATE ARGS
#define SI4455_CMD_ARG_COUNT_REQUEST_DEVICE_STATE                              1
//REQUEST_DEVICE_STATE REPLY
#define SI4455_CMD_REPLY_COUNT_REQUEST_DEVICE_STATE                            2
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_TYPE bitfield
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_SIZE 8
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_MASK 0xFF
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_MSB  7
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_LSB  0
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_INDEX 1
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_TYPE bitfield
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_SIZE 4
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_MASK 0x0F
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_MSB  3
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_LSB  0
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_INDEX 1
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_READY 3
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_READY2 4
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_TX 7
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_RX 8
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_TYPE u8
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_SIZE 8
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_MASK 0xFF
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_MSB  7
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_LSB  0
    #define SI4455_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_INDEX 2

#define SI4455_CMD_ID_CHANGE_STATE                                             0x34
//CHANGE_STATE ARGS
#define SI4455_CMD_ARG_COUNT_CHANGE_STATE                                      2
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_TYPE bitfield
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_SIZE 8
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_MASK 0xFF
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_MSB  7
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_LSB  0
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_INDEX 1
    #define SI4455_CMD_CHANGE_STATE_ARG_NEXT_STATE1_value (((cmd.arg.RAW[1])))
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_TYPE bitfield
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_SIZE 4
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_MASK 0x0F
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_MSB  3
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_LSB  0
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_INDEX 1
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_value (((cmd.arg.RAW[1]&0xF)))
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_NOCHANGE 0
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_SLEEP 1
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_SPI_ACTIVE 2
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_READY 3
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_READY2 4
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_TX_TUNE 5
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_RX_TUNE 6
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_TX 7
    #define SI4455_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_RX 8
//CHANGE_STATE REPLY
#define SI4455_CMD_REPLY_COUNT_CHANGE_STATE                                    0

#define SI4455_CMD_ID_READ_CMD_BUFF                                            0x44
//READ_CMD_BUFF ARGS
#define SI4455_CMD_ARG_COUNT_READ_CMD_BUFF                                     1
//READ_CMD_BUFF REPLY
#define SI4455_CMD_REPLY_COUNT_READ_CMD_BUFF                                   16
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_INDEX 1
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_INDEX 2
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_INDEX 3
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_INDEX 4
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_INDEX 5
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_INDEX 6
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_INDEX 7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_INDEX 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_INDEX 9
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_INDEX 10
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_INDEX 11
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_INDEX 12
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_INDEX 13
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_INDEX 14
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_INDEX 15
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_TYPE u8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_SIZE 8
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_MASK 0xFF
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_MSB  7
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_LSB  0
    #define SI4455_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_INDEX 16

#define SI4455_CMD_ID_FRR_A_READ                                               0x50
//FRR_A_READ ARGS
#define SI4455_CMD_ARG_COUNT_FRR_A_READ                                        1
//FRR_A_READ REPLY
#define SI4455_CMD_REPLY_COUNT_FRR_A_READ                                      4
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_TYPE u8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_SIZE 8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_MSB  7
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_LSB  0
    #define SI4455_CMD_FRR_A_READ_REP_FRR_B_VALUE_INDEX 1
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_TYPE u8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_SIZE 8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_MSB  7
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_LSB  0
    #define SI4455_CMD_FRR_A_READ_REP_FRR_C_VALUE_INDEX 2
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_TYPE u8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_SIZE 8
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_MSB  7
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_LSB  0
    #define SI4455_CMD_FRR_A_READ_REP_FRR_D_VALUE_INDEX 3

#define SI4455_CMD_ID_FRR_B_READ                                               0x51
//FRR_B_READ ARGS
#define SI4455_CMD_ARG_COUNT_FRR_B_READ                                        1
//FRR_B_READ REPLY
#define SI4455_CMD_REPLY_COUNT_FRR_B_READ                                      4
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_TYPE u8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_SIZE 8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_MSB  7
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_LSB  0
    #define SI4455_CMD_FRR_B_READ_REP_FRR_C_VALUE_INDEX 1
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_TYPE u8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_SIZE 8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_MSB  7
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_LSB  0
    #define SI4455_CMD_FRR_B_READ_REP_FRR_D_VALUE_INDEX 2
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_TYPE u8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_SIZE 8
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_MSB  7
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_LSB  0
    #define SI4455_CMD_FRR_B_READ_REP_FRR_A_VALUE_INDEX 3

#define SI4455_CMD_ID_FRR_C_READ                                               0x53
//FRR_C_READ ARGS
#define SI4455_CMD_ARG_COUNT_FRR_C_READ                                        1
//FRR_C_READ REPLY
#define SI4455_CMD_REPLY_COUNT_FRR_C_READ                                      4
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_TYPE u8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_SIZE 8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_MSB  7
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_LSB  0
    #define SI4455_CMD_FRR_C_READ_REP_FRR_D_VALUE_INDEX 1
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_TYPE u8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_SIZE 8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_MSB  7
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_LSB  0
    #define SI4455_CMD_FRR_C_READ_REP_FRR_A_VALUE_INDEX 2
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_TYPE u8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_SIZE 8
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_MSB  7
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_LSB  0
    #define SI4455_CMD_FRR_C_READ_REP_FRR_B_VALUE_INDEX 3

#define SI4455_CMD_ID_FRR_D_READ                                               0x57
//FRR_D_READ ARGS
#define SI4455_CMD_ARG_COUNT_FRR_D_READ                                        1
//FRR_D_READ REPLY
#define SI4455_CMD_REPLY_COUNT_FRR_D_READ                                      4
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_TYPE u8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_SIZE 8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_MSB  7
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_LSB  0
    #define SI4455_CMD_FRR_D_READ_REP_FRR_A_VALUE_INDEX 1
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_TYPE u8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_SIZE 8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_MSB  7
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_LSB  0
    #define SI4455_CMD_FRR_D_READ_REP_FRR_B_VALUE_INDEX 2
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_TYPE u8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_SIZE 8
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_MASK 0xFF
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_MSB  7
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_LSB  0
    #define SI4455_CMD_FRR_D_READ_REP_FRR_C_VALUE_INDEX 3

#define SI4455_CMD_ID_WRITE_TX_FIFO                                            0x66
//WRITE_TX_FIFO ARGS
#define SI4455_CMD_ARG_COUNT_WRITE_TX_FIFO                                     2
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_TYPE u8
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_SIZE 8
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_MASK 0xFF
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_MSB  7
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_LSB  0
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_INDEX 1
    #define SI4455_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_value (((cmd.arg.RAW[1])))
//WRITE_TX_FIFO REPLY
#define SI4455_CMD_REPLY_COUNT_WRITE_TX_FIFO                                   0

#define SI4455_CMD_ID_READ_RX_FIFO                                             0x77
//READ_RX_FIFO ARGS
#define SI4455_CMD_ARG_COUNT_READ_RX_FIFO                                      1
//READ_RX_FIFO REPLY
#define SI4455_CMD_REPLY_COUNT_READ_RX_FIFO                                    0


// Property group Id defines.
#define SI4455_PROP_GRP_ID_FRR_CTL                                             2
#define SI4455_PROP_GRP_ID_MATCH                                               48
#define SI4455_PROP_GRP_ID_EZCONFIG                                            36
#define SI4455_PROP_GRP_ID_PA                                                  34
#define SI4455_PROP_GRP_ID_SYNC                                                17
#define SI4455_PROP_GRP_ID_INT_CTL                                             1
#define SI4455_PROP_GRP_ID_OTP_VARS                                            242
#define SI4455_PROP_GRP_ID_FREQ_CONTROL                                        64

// Property group length defines.
#define SI4455_PROP_GRP_LEN_FRR_CTL                                            4
#define SI4455_PROP_GRP_LEN_MATCH                                              12
#define SI4455_PROP_GRP_LEN_EZCONFIG                                           4
#define SI4455_PROP_GRP_LEN_PA                                                 6
#define SI4455_PROP_GRP_LEN_SYNC                                               5
#define SI4455_PROP_GRP_LEN_INT_CTL                                            4
#define SI4455_PROP_GRP_LEN_OTP_VARS                                           45
#define SI4455_PROP_GRP_LEN_FREQ_CONTROL                                       8

// Property index within a group defines.
#define SI4455_PROP_GRP_INDEX_FRR_CTL_A_MODE                                   0
#define SI4455_PROP_GRP_INDEX_FRR_CTL_B_MODE                                   1
#define SI4455_PROP_GRP_INDEX_FRR_CTL_C_MODE                                   2
#define SI4455_PROP_GRP_INDEX_FRR_CTL_D_MODE                                   3

#define SI4455_PROP_GRP_INDEX_MATCH_VALUE_1                                    0
#define SI4455_PROP_GRP_INDEX_MATCH_MASK_1                                     1
#define SI4455_PROP_GRP_INDEX_MATCH_CTRL_1                                     2
#define SI4455_PROP_GRP_INDEX_MATCH_VALUE_2                                    3
#define SI4455_PROP_GRP_INDEX_MATCH_MASK_2                                     4
#define SI4455_PROP_GRP_INDEX_MATCH_CTRL_2                                     5
#define SI4455_PROP_GRP_INDEX_MATCH_VALUE_3                                    6
#define SI4455_PROP_GRP_INDEX_MATCH_MASK_3                                     7
#define SI4455_PROP_GRP_INDEX_MATCH_CTRL_3                                     8
#define SI4455_PROP_GRP_INDEX_MATCH_VALUE_4                                    9
#define SI4455_PROP_GRP_INDEX_MATCH_MASK_4                                     10
#define SI4455_PROP_GRP_INDEX_MATCH_CTRL_4                                     11

#define SI4455_PROP_GRP_INDEX_EZCONFIG_MODULATION                              0
#define SI4455_PROP_GRP_INDEX_EZCONFIG_CONFIG_SELECT                           1
#define SI4455_PROP_GRP_INDEX_EZCONFIG_PKT                                     2
#define SI4455_PROP_GRP_INDEX_EZCONFIG_XO_TUNE                                 3
#define SI4455_PROP_GRP_INDEX_EZCONFIG_SPARE0                                  4
#define SI4455_PROP_GRP_INDEX_EZCONFIG_SPARE1                                  5
#define SI4455_PROP_GRP_INDEX_EZCONFIG_SPARE2                                  6
#define SI4455_PROP_GRP_INDEX_EZCONFIG_SPARE3                                  7
#define SI4455_PROP_GRP_INDEX_EZCONFIG_SPARE4                                  8

#define SI4455_PROP_GRP_INDEX_PA_PAD0                                          6
#define SI4455_PROP_GRP_INDEX_PA_PWR_LVL                                       1
#define SI4455_PROP_GRP_INDEX_PA_BIAS_CLKDUTY                                  2
#define SI4455_PROP_GRP_INDEX_PA_TC                                            3
#define SI4455_PROP_GRP_INDEX_PA_RAMP_EX                                       4
#define SI4455_PROP_GRP_INDEX_PA_RAMP_DOWN_DELAY                               5

#define SI4455_PROP_GRP_INDEX_SYNC_CONFIG                                      0
#define SI4455_PROP_GRP_INDEX_SYNC_BITS_31_24                                  1
#define SI4455_PROP_GRP_INDEX_SYNC_BITS_23_16                                  2
#define SI4455_PROP_GRP_INDEX_SYNC_BITS_15_8                                   3
#define SI4455_PROP_GRP_INDEX_SYNC_BITS_7_0                                    4

#define SI4455_PROP_GRP_INDEX_INT_CTL_ENABLE                                   0
#define SI4455_PROP_GRP_INDEX_INT_CTL_PH_ENABLE                                1
#define SI4455_PROP_GRP_INDEX_INT_CTL_MODEM_ENABLE                             2
#define SI4455_PROP_GRP_INDEX_INT_CTL_CHIP_ENABLE                              3

#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_INTE                                0
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_2                              1
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_1                              2
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_0                              3
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_CHANNEL_STEP_SIZE_1                 4
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_CHANNEL_STEP_SIZE_0                 5
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_W_SIZE                              6
#define SI4455_PROP_GRP_INDEX_FREQ_CONTROL_VCOCNT_RX_ADJ                       7

// Defines for fields within the properties.
#define SI4455_PROP_INT_CTL_ENABLE_MASK                                        0xFF
#define SI4455_PROP_INT_CTL_ENABLE_DEFAULT                                     0x04
#define SI4455_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_SIZE                     1
#define SI4455_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_LSB                      2
#define SI4455_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_MSB                      2
#define SI4455_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_MASK                     0x4
#define SI4455_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_BIT                      0x4
#define SI4455_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_SIZE                    1
#define SI4455_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_LSB                     1
#define SI4455_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_MSB                     1
#define SI4455_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_MASK                    0x2
#define SI4455_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_BIT                     0x2
#define SI4455_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_SIZE                       1
#define SI4455_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_LSB                        0
#define SI4455_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_MSB                        0
#define SI4455_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_MASK                       0x1
#define SI4455_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_BIT                        0x1

#define SI4455_PROP_INT_CTL_PH_ENABLE_MASK                                     0xFF
#define SI4455_PROP_INT_CTL_PH_ENABLE_DEFAULT                                  0x00
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_SIZE                      1
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_LSB                       5
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_MSB                       5
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_MASK                      0x20
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_BIT                       0x20
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_SIZE                        1
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_LSB                         4
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_MSB                         4
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_MASK                        0x10
#define SI4455_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_BIT                         0x10
#define SI4455_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_SIZE                        1
#define SI4455_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_LSB                         3
#define SI4455_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_MSB                         3
#define SI4455_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_MASK                        0x8
#define SI4455_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_BIT                         0x8
#define SI4455_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_SIZE             1
#define SI4455_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_LSB              1
#define SI4455_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_MSB              1
#define SI4455_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_MASK             0x2
#define SI4455_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_BIT              0x2
#define SI4455_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_SIZE              1
#define SI4455_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_LSB               0
#define SI4455_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_MSB               0
#define SI4455_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_MASK              0x1
#define SI4455_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_BIT               0x1

#define SI4455_PROP_INT_CTL_MODEM_ENABLE_MASK                                  0xFF
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_DEFAULT                               0x00
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_SIZE              1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_LSB               6
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_MSB               6
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_MASK              0x40
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_BIT               0x40
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_SIZE                  1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_LSB                   5
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_MSB                   5
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_MASK                  0x20
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_BIT                   0x20
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_SIZE                     1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_LSB                      4
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_MSB                      4
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_MASK                     0x10
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_BIT                      0x10
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_SIZE                          1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_LSB                           3
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_MSB                           3
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_MASK                          0x8
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_BIT                           0x8
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_SIZE              1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_LSB               2
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_MSB               2
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_MASK              0x4
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_BIT               0x4
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_SIZE               1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_LSB                1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_MSB                1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_MASK               0x2
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_BIT                0x2
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_SIZE                   1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_LSB                    0
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_MSB                    0
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_MASK                   0x1
#define SI4455_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_BIT                    0x1

#define SI4455_PROP_INT_CTL_CHIP_ENABLE_MASK                                   0xFF
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_DEFAULT                                0x04
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_SIZE                            1
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_LSB                             6
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_MSB                             6
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_MASK                            0x40
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_BIT                             0x40
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_SIZE  1
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_LSB   5
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_MSB   5
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_MASK  0x20
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_BIT   0x20
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_SIZE                   1
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_LSB                    4
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_MSB                    4
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_MASK                   0x10
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_BIT                    0x10
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_SIZE                      1
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_LSB                       3
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_MSB                       3
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_MASK                      0x8
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_BIT                       0x8
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_SIZE                     1
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_LSB                      2
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_MSB                      2
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_MASK                     0x4
#define SI4455_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_BIT                      0x4

#define SI4455_PROP_FRR_CTL_A_MODE_MASK                                        0xFF
#define SI4455_PROP_FRR_CTL_A_MODE_DEFAULT                                     0x01
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_SIZE                             8
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_LSB                              0
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_MSB                              7
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_MASK                             0xFF
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_DISABLED                    0
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_STATUS                  1
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PEND                    2
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PH_STATUS               3
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PH_PEND                 4
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_MODEM_STATUS            5
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_MODEM_PEND              6
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_CHIP_STATUS             7
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_CHIP_PEND               8
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_CURRENT_STATE               9
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_LATCHED_RSSI                10
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE0                      11
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE1                      12
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE2                      13
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE3                      14
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE4                      15
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE5                      16
#define SI4455_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE6                      17

#define SI4455_PROP_FRR_CTL_B_MODE_MASK                                        0xFF
#define SI4455_PROP_FRR_CTL_B_MODE_DEFAULT                                     0x02
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_SIZE                             8
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_LSB                              0
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_MSB                              7
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_MASK                             0xFF
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_DISABLED                    0
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_STATUS                  1
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PEND                    2
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PH_STATUS               3
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PH_PEND                 4
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_MODEM_STATUS            5
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_MODEM_PEND              6
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_CHIP_STATUS             7
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_CHIP_PEND               8
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_CURRENT_STATE               9
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_LATCHED_RSSI                10
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE0                      11
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE1                      12
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE2                      13
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE3                      14
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE4                      15
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE5                      16
#define SI4455_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE6                      17

#define SI4455_PROP_FRR_CTL_C_MODE_MASK                                        0xFF
#define SI4455_PROP_FRR_CTL_C_MODE_DEFAULT                                     0x09
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_SIZE                             8
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_LSB                              0
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_MSB                              7
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_MASK                             0xFF
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_DISABLED                    0
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_STATUS                  1
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PEND                    2
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PH_STATUS               3
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PH_PEND                 4
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_MODEM_STATUS            5
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_MODEM_PEND              6
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_CHIP_STATUS             7
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_CHIP_PEND               8
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_CURRENT_STATE               9
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_LATCHED_RSSI                10
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE0                      11
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE1                      12
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE2                      13
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE3                      14
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE4                      15
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE5                      16
#define SI4455_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE6                      17

#define SI4455_PROP_FRR_CTL_D_MODE_MASK                                        0xFF
#define SI4455_PROP_FRR_CTL_D_MODE_DEFAULT                                     0x00
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_SIZE                             8
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_LSB                              0
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_MSB                              7
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_MASK                             0xFF
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_DISABLED                    0
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_STATUS                  1
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_PEND                    2
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_PH_STATUS               3
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_PH_PEND                 4
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_MODEM_STATUS            5
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_MODEM_PEND              6
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_CHIP_STATUS             7
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_INT_CHIP_PEND               8
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_CURRENT_STATE               9
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_LATCHED_RSSI                10
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE0                      11
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE1                      12
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE2                      13
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE3                      14
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE4                      15
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE5                      16
#define SI4455_PROP_FRR_CTL_D_MODE_FRR_D_MODE_ENUM_SPARE6                      17

#define SI4455_PROP_SYNC_BITS_31_24_MASK                                       0xFF
#define SI4455_PROP_SYNC_BITS_31_24_DEFAULT                                    0x2D
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_SIZE                            8
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_LSB                             0
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_MSB                             7
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_MIN                             0
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_MAX                             0xff
#define SI4455_PROP_SYNC_BITS_31_24_BITS_31_24_MASK                            0xFF

#define SI4455_PROP_SYNC_BITS_23_16_MASK                                       0xFF
#define SI4455_PROP_SYNC_BITS_23_16_DEFAULT                                    0xD4
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_SIZE                            8
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_LSB                             0
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_MSB                             7
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_MIN                             0
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_MAX                             0xff
#define SI4455_PROP_SYNC_BITS_23_16_BITS_23_16_MASK                            0xFF

#define SI4455_PROP_SYNC_BITS_15_8_MASK                                        0xFF
#define SI4455_PROP_SYNC_BITS_15_8_DEFAULT                                     0x2D
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_SIZE                              8
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_LSB                               0
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_MSB                               7
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_MIN                               0
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_MAX                               0xff
#define SI4455_PROP_SYNC_BITS_15_8_BITS_15_8_MASK                              0xFF

#define SI4455_PROP_SYNC_BITS_7_0_MASK                                         0xFF
#define SI4455_PROP_SYNC_BITS_7_0_DEFAULT                                      0xD4
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_SIZE                                8
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_LSB                                 0
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_MSB                                 7
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_MIN                                 0
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_MAX                                 0xff
#define SI4455_PROP_SYNC_BITS_7_0_BITS_7_0_MASK                                0xFF

#define SI4455_PROP_PA_PWR_LVL_MASK                                            0xFF
#define SI4455_PROP_PA_PWR_LVL_DEFAULT                                         0x7F
#define SI4455_PROP_PA_PWR_LVL_DDAC_SIZE                                       7
#define SI4455_PROP_PA_PWR_LVL_DDAC_LSB                                        0
#define SI4455_PROP_PA_PWR_LVL_DDAC_MSB                                        6
#define SI4455_PROP_PA_PWR_LVL_DDAC_MIN                                        0
#define SI4455_PROP_PA_PWR_LVL_DDAC_MAX                                        127
#define SI4455_PROP_PA_PWR_LVL_DDAC_MASK                                       0x7F

#define SI4455_PROP_PA_BIAS_CLKDUTY_MASK                                       0xFF
#define SI4455_PROP_PA_BIAS_CLKDUTY_DEFAULT                                    0x00
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_SIZE                              2
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_LSB                               6
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_MSB                               7
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_MASK                              0xC0
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_DIFF_50                      0
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_DIFF_25                      1
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_SINGLE_50                    2
#define SI4455_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_SINGLE_25                    3
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_SIZE                                    6
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_LSB                                     0
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_MSB                                     5
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_MIN                                     0
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_MAX                                     63
#define SI4455_PROP_PA_BIAS_CLKDUTY_OB_MASK                                    0x3F

#define SI4455_PROP_PA_TC_MASK                                                 0xFF
#define SI4455_PROP_PA_TC_DEFAULT                                              0x5D
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_SIZE                                     3
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_LSB                                      5
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_MSB                                      7
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_MASK                                     0xE0
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_2_US                                0
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_6_US                                1
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_10_US                               2
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_14_US                               3
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_18_US                               4
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_22_US                               5
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_26_US                               6
#define SI4455_PROP_PA_TC_FSK_MOD_DLY_ENUM_30_US                               7
#define SI4455_PROP_PA_TC_TC_SIZE                                              5
#define SI4455_PROP_PA_TC_TC_LSB                                               0
#define SI4455_PROP_PA_TC_TC_MSB                                               4
#define SI4455_PROP_PA_TC_TC_MIN                                               0
#define SI4455_PROP_PA_TC_TC_MAX                                               31
#define SI4455_PROP_PA_TC_TC_MASK                                              0x1F

#define SI4455_PROP_PA_RAMP_EX_MASK                                            0xFF
#define SI4455_PROP_PA_RAMP_EX_DEFAULT                                         0x00
#define SI4455_PROP_PA_RAMP_EX_VSET_SIZE                                       4
#define SI4455_PROP_PA_RAMP_EX_VSET_LSB                                        4
#define SI4455_PROP_PA_RAMP_EX_VSET_MSB                                        7
#define SI4455_PROP_PA_RAMP_EX_VSET_MIN                                        0
#define SI4455_PROP_PA_RAMP_EX_VSET_MAX                                        15
#define SI4455_PROP_PA_RAMP_EX_VSET_MASK                                       0xF0
#define SI4455_PROP_PA_RAMP_EX_TC_SIZE                                         4
#define SI4455_PROP_PA_RAMP_EX_TC_LSB                                          0
#define SI4455_PROP_PA_RAMP_EX_TC_MSB                                          3
#define SI4455_PROP_PA_RAMP_EX_TC_MIN                                          0
#define SI4455_PROP_PA_RAMP_EX_TC_MAX                                          15
#define SI4455_PROP_PA_RAMP_EX_TC_MASK                                         0xF

#define SI4455_PROP_PA_RAMP_DOWN_DELAY_MASK                                    0xFF
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_DEFAULT                                 0x23
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_SIZE                    8
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_LSB                     0
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MSB                     7
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MIN                     1
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MAX                     40
#define SI4455_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MASK                    0xFF

#define SI4455_PROP_EZCONFIG_MODULATION_MASK                                   0xFF
#define SI4455_PROP_EZCONFIG_MODULATION_DEFAULT                                0x02
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_SIZE               1
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_LSB                7
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_MSB                7
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_MASK               0x80
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_BIT                0x80
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_ENUM_SYNC          0
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_TYPE_ENUM_ASYNC         1
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_SIZE               2
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_LSB                5
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_MSB                6
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_MASK               0x60
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_ENUM_GPIO0         0
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_ENUM_GPIO1         1
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_ENUM_GPIO2         2
#define SI4455_PROP_EZCONFIG_MODULATION_TX_DIRECT_MODE_GPIO_ENUM_GPIO3         3
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_SIZE                        2
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_LSB                         3
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_MSB                         4
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_MASK                        0x18
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_ENUM_PACKET                 0
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_ENUM_DIRECT                 1
#define SI4455_PROP_EZCONFIG_MODULATION_MOD_SOURCE_ENUM_PSEUDO                 2

#define SI4455_PROP_EZCONFIG_XO_TUNE_MASK                                      0xFF
#define SI4455_PROP_EZCONFIG_XO_TUNE_DEFAULT                                   0x40
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_SIZE                           7
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_LSB                            0
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_MSB                            6
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_MASK                           0x7F
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_ENUM_FASTEST_FREQUENCY         0
#define SI4455_PROP_EZCONFIG_XO_TUNE_TUNE_VALUE_ENUM_SLOWEST_FREQUENCY         127

#define SI4455_PROP_MATCH_VALUE_1_MASK                                         0xFF
#define SI4455_PROP_MATCH_VALUE_1_DEFAULT                                      0x00
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_SIZE                                 8
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_LSB                                  0
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_MSB                                  7
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_MIN                                  0
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_MAX                                  0xFF
#define SI4455_PROP_MATCH_VALUE_1_VALUE_1_MASK                                 0xFF

#define SI4455_PROP_MATCH_MASK_1_MASK                                          0xFF
#define SI4455_PROP_MATCH_MASK_1_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_MASK_1_MASK_1_SIZE                                   8
#define SI4455_PROP_MATCH_MASK_1_MASK_1_LSB                                    0
#define SI4455_PROP_MATCH_MASK_1_MASK_1_MSB                                    7
#define SI4455_PROP_MATCH_MASK_1_MASK_1_MIN                                    0
#define SI4455_PROP_MATCH_MASK_1_MASK_1_MAX                                    0xFF
#define SI4455_PROP_MATCH_MASK_1_MASK_1_MASK                                   0xFF

#define SI4455_PROP_MATCH_CTRL_1_MASK                                          0xFF
#define SI4455_PROP_MATCH_CTRL_1_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_CTRL_1_POLARITY_SIZE                                 1
#define SI4455_PROP_MATCH_CTRL_1_POLARITY_LSB                                  7
#define SI4455_PROP_MATCH_CTRL_1_POLARITY_MSB                                  7
#define SI4455_PROP_MATCH_CTRL_1_POLARITY_MASK                                 0x80
#define SI4455_PROP_MATCH_CTRL_1_POLARITY_BIT                                  0x80
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_SIZE                                 1
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_LSB                                  6
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_MSB                                  6
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_MASK                                 0x40
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_BIT                                  0x40
#define SI4455_PROP_MATCH_CTRL_1_MATCH_EN_ENUM_MATCH_ENABLE                    1
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_SIZE                                   5
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_LSB                                    0
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_MSB                                    4
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_MIN                                    0
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_MAX                                    0x1F
#define SI4455_PROP_MATCH_CTRL_1_OFFSET_MASK                                   0x1F

#define SI4455_PROP_MATCH_VALUE_2_MASK                                         0xFF
#define SI4455_PROP_MATCH_VALUE_2_DEFAULT                                      0x00
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_SIZE                                 8
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_LSB                                  0
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_MSB                                  7
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_MIN                                  0
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_MAX                                  0xFF
#define SI4455_PROP_MATCH_VALUE_2_VALUE_2_MASK                                 0xFF

#define SI4455_PROP_MATCH_MASK_2_MASK                                          0xFF
#define SI4455_PROP_MATCH_MASK_2_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_MASK_2_MASK_2_SIZE                                   8
#define SI4455_PROP_MATCH_MASK_2_MASK_2_LSB                                    0
#define SI4455_PROP_MATCH_MASK_2_MASK_2_MSB                                    7
#define SI4455_PROP_MATCH_MASK_2_MASK_2_MIN                                    0
#define SI4455_PROP_MATCH_MASK_2_MASK_2_MAX                                    0xFF
#define SI4455_PROP_MATCH_MASK_2_MASK_2_MASK                                   0xFF

#define SI4455_PROP_MATCH_CTRL_2_MASK                                          0xFF
#define SI4455_PROP_MATCH_CTRL_2_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_CTRL_2_POLARITY_SIZE                                 1
#define SI4455_PROP_MATCH_CTRL_2_POLARITY_LSB                                  7
#define SI4455_PROP_MATCH_CTRL_2_POLARITY_MSB                                  7
#define SI4455_PROP_MATCH_CTRL_2_POLARITY_MASK                                 0x80
#define SI4455_PROP_MATCH_CTRL_2_POLARITY_BIT                                  0x80
#define SI4455_PROP_MATCH_CTRL_2_LOGIC_SIZE                                    1
#define SI4455_PROP_MATCH_CTRL_2_LOGIC_LSB                                     6
#define SI4455_PROP_MATCH_CTRL_2_LOGIC_MSB                                     6
#define SI4455_PROP_MATCH_CTRL_2_LOGIC_MASK                                    0x40
#define SI4455_PROP_MATCH_CTRL_2_LOGIC_BIT                                     0x40
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_SIZE                                   5
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_LSB                                    0
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_MSB                                    4
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_MIN                                    0
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_MAX                                    0x1F
#define SI4455_PROP_MATCH_CTRL_2_OFFSET_MASK                                   0x1F

#define SI4455_PROP_MATCH_VALUE_3_MASK                                         0xFF
#define SI4455_PROP_MATCH_VALUE_3_DEFAULT                                      0x00
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_SIZE                                 8
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_LSB                                  0
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_MSB                                  7
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_MIN                                  0
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_MAX                                  0xFF
#define SI4455_PROP_MATCH_VALUE_3_VALUE_3_MASK                                 0xFF

#define SI4455_PROP_MATCH_MASK_3_MASK                                          0xFF
#define SI4455_PROP_MATCH_MASK_3_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_MASK_3_MASK_3_SIZE                                   8
#define SI4455_PROP_MATCH_MASK_3_MASK_3_LSB                                    0
#define SI4455_PROP_MATCH_MASK_3_MASK_3_MSB                                    7
#define SI4455_PROP_MATCH_MASK_3_MASK_3_MIN                                    0
#define SI4455_PROP_MATCH_MASK_3_MASK_3_MAX                                    0xFF
#define SI4455_PROP_MATCH_MASK_3_MASK_3_MASK                                   0xFF

#define SI4455_PROP_MATCH_CTRL_3_MASK                                          0xFF
#define SI4455_PROP_MATCH_CTRL_3_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_CTRL_3_POLARITY_SIZE                                 1
#define SI4455_PROP_MATCH_CTRL_3_POLARITY_LSB                                  7
#define SI4455_PROP_MATCH_CTRL_3_POLARITY_MSB                                  7
#define SI4455_PROP_MATCH_CTRL_3_POLARITY_MASK                                 0x80
#define SI4455_PROP_MATCH_CTRL_3_POLARITY_BIT                                  0x80
#define SI4455_PROP_MATCH_CTRL_3_LOGIC_SIZE                                    1
#define SI4455_PROP_MATCH_CTRL_3_LOGIC_LSB                                     6
#define SI4455_PROP_MATCH_CTRL_3_LOGIC_MSB                                     6
#define SI4455_PROP_MATCH_CTRL_3_LOGIC_MASK                                    0x40
#define SI4455_PROP_MATCH_CTRL_3_LOGIC_BIT                                     0x40
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_SIZE                                   5
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_LSB                                    0
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_MSB                                    4
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_MIN                                    0
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_MAX                                    0x1F
#define SI4455_PROP_MATCH_CTRL_3_OFFSET_MASK                                   0x1F

#define SI4455_PROP_MATCH_VALUE_4_MASK                                         0xFF
#define SI4455_PROP_MATCH_VALUE_4_DEFAULT                                      0x00
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_SIZE                                 8
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_LSB                                  0
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_MSB                                  7
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_MIN                                  0
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_MAX                                  0xFF
#define SI4455_PROP_MATCH_VALUE_4_VALUE_4_MASK                                 0xFF

#define SI4455_PROP_MATCH_MASK_4_MASK                                          0xFF
#define SI4455_PROP_MATCH_MASK_4_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_MASK_4_MASK_4_SIZE                                   8
#define SI4455_PROP_MATCH_MASK_4_MASK_4_LSB                                    0
#define SI4455_PROP_MATCH_MASK_4_MASK_4_MSB                                    7
#define SI4455_PROP_MATCH_MASK_4_MASK_4_MIN                                    0
#define SI4455_PROP_MATCH_MASK_4_MASK_4_MAX                                    0xFF
#define SI4455_PROP_MATCH_MASK_4_MASK_4_MASK                                   0xFF

#define SI4455_PROP_MATCH_CTRL_4_MASK                                          0xFF
#define SI4455_PROP_MATCH_CTRL_4_DEFAULT                                       0x00
#define SI4455_PROP_MATCH_CTRL_4_POLARITY_SIZE                                 1
#define SI4455_PROP_MATCH_CTRL_4_POLARITY_LSB                                  7
#define SI4455_PROP_MATCH_CTRL_4_POLARITY_MSB                                  7
#define SI4455_PROP_MATCH_CTRL_4_POLARITY_MASK                                 0x80
#define SI4455_PROP_MATCH_CTRL_4_POLARITY_BIT                                  0x80
#define SI4455_PROP_MATCH_CTRL_4_LOGIC_SIZE                                    1
#define SI4455_PROP_MATCH_CTRL_4_LOGIC_LSB                                     6
#define SI4455_PROP_MATCH_CTRL_4_LOGIC_MSB                                     6
#define SI4455_PROP_MATCH_CTRL_4_LOGIC_MASK                                    0x40
#define SI4455_PROP_MATCH_CTRL_4_LOGIC_BIT                                     0x40
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_SIZE                                   5
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_LSB                                    0
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_MSB                                    4
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_MIN                                    0
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_MAX                                    0x1F
#define SI4455_PROP_MATCH_CTRL_4_OFFSET_MASK                                   0x1F

#define SI4455_PROP_FREQ_CONTROL_INTE_MASK                                     0xFF
#define SI4455_PROP_FREQ_CONTROL_INTE_DEFAULT                                  0x3C
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_SIZE                                7
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_LSB                                 0
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_MSB                                 6
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_MIN                                 0
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_MAX                                 127
#define SI4455_PROP_FREQ_CONTROL_INTE_INTE_MASK                                0x7F

#define SI4455_PROP_FREQ_CONTROL_FRAC_2_MASK                                   0xFF
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_DEFAULT                                0x08
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_SIZE                            3
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_LSB                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MSB                             2
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MIN                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MAX                             7
#define SI4455_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MASK                            0x7

#define SI4455_PROP_FREQ_CONTROL_FRAC_1_MASK                                   0xFF
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_DEFAULT                                0x00
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_SIZE                            8
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_LSB                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MSB                             7
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MIN                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MAX                             255
#define SI4455_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MASK                            0xFF

#define SI4455_PROP_FREQ_CONTROL_FRAC_0_MASK                                   0xFF
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_DEFAULT                                0x00
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_SIZE                            8
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_LSB                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MSB                             7
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MIN                             0
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MAX                             255
#define SI4455_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MASK                            0xFF

#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_MASK                      0xFF
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_DEFAULT                   0x00
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_SIZE  8
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_LSB   0
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MSB   7
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MIN   0
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MAX   255
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MASK  0xFF

#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_MASK                      0xFF
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_DEFAULT                   0x00
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_SIZE  8
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_LSB   0
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MSB   7
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MIN   0
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MAX   255
#define SI4455_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MASK  0xFF

#define SI4455_PROP_FREQ_CONTROL_W_SIZE_MASK                                   0xFF
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_DEFAULT                                0x20
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_SIZE                            8
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_LSB                             0
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MSB                             7
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MIN                             0
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MAX                             255
#define SI4455_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MASK                            0xFF

#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_MASK                            0xFF
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_DEFAULT                         0xFF
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_SIZE              8
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_LSB               0
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MSB               7
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MIN               -128
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MAX               127
#define SI4455_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MASK              0xFF

#endif // _SI4455_DEFS_H_