EVE 1.0
startup-efm32.c
1 #include <stdio.h>
2 #include <stdint.h>
3 #include <em_device.h>
4 #include <core_cm3.h>
5 #include <em_mpu.h>
6 #include <em_cmu.h>
7 #include <em_dbg.h>
8 #include <gpiointerrupt.h>
9 #include <core/clk.h>
10 #include <contiki-conf.h>
11 
12 extern uint8_t __bss_start__[];
13 extern uint8_t __bss_end__[];
14 extern uint32_t __isr_vector[];
15 
16 void _start(void) /*__attribute__((naked))*/;
17 
18 extern int main(void);
19 
20 static void
21 clear_bss(void)
22 {
23  uint8_t *m = __bss_start__;
24  while(m < __bss_end__) {
25  *m++ = 0;
26  }
27 }
28 
29 static void
30 enable_fault_exceptions(void)
31 {
32 #if 0
33  MPU_RegionInit_TypeDef flashInit = MPU_INIT_FLASH_DEFAULT;
34  MPU_RegionInit_TypeDef sramInit = MPU_INIT_SRAM_DEFAULT;
35  MPU_RegionInit_TypeDef peripheralInit = MPU_INIT_PERIPHERAL_DEFAULT;
36 
37  MPU_Disable();
38  /* TODO: Configure regions */
39  MPU_ConfigureRegion(&flashInit);
40  MPU_ConfigureRegion(&sramInit);
41  MPU_ConfigureRegion(&peripheralInit);
42  MPU_Enable(MPU_CTRL_PRIVDEFENA);
43 
44  SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
45  | SCB_SHCSR_USGFAULTENA_Msk);
46 #endif
47 }
48 
49 static void
50 select_clocks()
51 {
52  /* Starting LFRCO and waiting until it is stable */
53  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
54  CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
55 
56  /* Routing the LFRCO clock to the LF doamains A and B */
57  CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO);
58  CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO);
59  CMU_ClockEnable(cmuClock_CORELE, true);
60 
61  /* Enable and select 1 MHz HF clock. Application will
62  * change it later by platform framework.*/
63  CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO);
64  CMU_HFRCOBandSet(cmuHFRCOBand_1MHz);
65 }
66 
67 #ifdef EFM32_DEBUG_SWO
68 static void setupSWO(void)
69 {
70  /* Enable GPIO Clock. */
71  CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
72  /* Enable Serial wire output pin */
73  GPIO->ROUTE |= GPIO_ROUTE_SWOPEN;
74 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) || defined(_EFM32_LEOPARD_FAMILY)
75  /* Set location 0 */
76  GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC0;
77 
78  /* Enable output on pin - GPIO Port F, Pin 2 */
79  GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK);
80  GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL;
81 #else
82  /* Set location 1 */
83  GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC1;
84  /* Enable output on pin */
85  GPIO->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
86  GPIO->P[2].MODEH |= GPIO_P_MODEH_MODE15_PUSHPULL;
87 #endif
88  /* Enable debug clock AUXHFRCO */
89  CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
90 
91  while(!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
92 
93  /* Enable trace in core debug */
94  CoreDebug->DHCSR |= 1;
95  CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
96 
97  /* Enable PC and IRQ sampling output */
98  DWT->CTRL = 0x400113FF;
99  /* Set TPIU prescaler to 16. */
100  TPI->ACPR = 0xf;
101  /* Set protocol to NRZ */
102  TPI->SPPR = 2;
103  /* Unlock ITM and output data */
104  ITM->LAR = 0xC5ACCE55;
105  ITM->TCR = 0x10009;
106 
107  /* Disable GPIO Clock. */
108  CMU->HFPERCLKEN0 &= ~CMU_HFPERCLKEN0_GPIO;
109 }
110 #endif /* EFM32_DEBUG_SWO */
111 
112 void __attribute__((naked))
113 _start(void)
114 {
115  /* Init stack pointer */
116  asm (
117  "ldr r3, =__isr_vector;"
118  "ldr sp, [r3];"
119  );
120 
121  /* Skip bootloader */
122  SCB->VTOR = (uint32_t)__isr_vector;
123 
124  /* Setup core interrupt priorities */
125  NVIC_SetPriority(PendSV_IRQn, 0xFF);
126 
127  clear_bss();
128  enable_fault_exceptions();
129  select_clocks();
130 
131  /* System tick counter is used by uwork */
132  CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
133  DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
134 
135 #ifdef EFM32_DEBUG_SWO
136  if (DBG_Connected())
137  {
138  setupSWO();
139  }
140 #endif
141 
142  GPIOINT_Init();
143 
144  main();
145  while(1);
146 }
147 
148 void
149 _xassert(const char *file, int lineno)
150 {
151  printf("Assertion failed: file %s, line %d.\n", file, lineno);
152  /*
153  * loop for a while;
154  * call _reset_vector__();
155  */
156  while(1);
157 }
158 
159 void uip_log(char *msg)
160 {
161  printf("UIP: %s\r\n", msg);
162 }
163 
164 /* TODO: Implement handlers */
165 void
166 NMI_Handler(void)
167 {
168  while(1);
169 }
170 
171 void
172 HardFault_Handler(void)
173 {
174  while(1);
175 }
176 
177 void
178 UsageFault_Handler(void)
179 {
180  while(1);
181 }
182 
183 void
184 MemManage_Handler(void)
185 {
186  while(1);
187 }
188 
189 void
190 BusFault_Handler(void)
191 {
192  while(1);
193 }
void uip_log(char *msg)
__attribute__((always_inline)) static inline void swint_enable_indirect_adapter(swint_state_t *state)
Definition: work.h:245
Header file for the EVE clock management framework.