startup-nrf52.c

#include <stdio.h>
#include <stdint.h>
#include <dev/nvram.h>
#include <core/clk.h>
#include <core/uwork.h>
#include <contiki-conf.h>
#include <debug-uart.h>
#include <nrf_soc.h>

extern uint8_t __bss_start__[];
extern uint8_t __bss_end__[];
extern uint32_t __isr_vector[];
extern void (*__preinit_array_start []) (void);
extern void (*__preinit_array_end []) (void);
extern void (*__init_array_start []) (void);
extern void (*__init_array_end []) (void);

void _start(void) /*__attribute__((naked))*/;

extern int main(void);

static void
clear_bss(void)
{
  uint8_t *m = __bss_start__;
  while(m < __bss_end__) {
    *m++ = 0;
  }
}

static void
enable_fault_exceptions(void)
{
#if 0
  MPU_RegionInit_TypeDef flashInit       = MPU_INIT_FLASH_DEFAULT;
  MPU_RegionInit_TypeDef sramInit        = MPU_INIT_SRAM_DEFAULT;
  MPU_RegionInit_TypeDef peripheralInit  = MPU_INIT_PERIPHERAL_DEFAULT;

  MPU_Disable();
  /* TODO: Configure regions */
  MPU_ConfigureRegion(&flashInit);
  MPU_ConfigureRegion(&sramInit);
  MPU_ConfigureRegion(&peripheralInit);
  MPU_Enable(MPU_CTRL_PRIVDEFENA);

  SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
     | SCB_SHCSR_USGFAULTENA_Msk);
#endif
}

static void
select_clocks()
{
}

#ifdef NRF52_ENABLE_SWO
static void setupSWO(void)
{
  NRF_CLOCK->TRACECONFIG |= (CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos);
  NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos)
      | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
      | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
}
#endif /* NRF52_ENABLE_SWO */

static void libc_init(void)
{
  unsigned Index, Count;

  Count = __preinit_array_end - __preinit_array_start;
  for (Index = 0; Index < Count; Index++)
    __preinit_array_start[Index]();

  Count = __init_array_end - __init_array_start;
  for (Index = 0; Index < Count; Index++)
    __init_array_start[Index]();
}

void __attribute__((naked))
_start(void)
{
  /* Init stack pointer */
  __asm__ (
    "ldr r3, =__isr_vector;"
    "ldr sp, [r3];"
  );

  /* Enable DC/DC */
  //NRF_POWER->DCDCEN = POWER_DCDCEN_DCDCEN_Enabled;

  /* Setup core interrupt priorities */
  NVIC_SetPriority(PendSV_IRQn, 0xFF);

#ifdef NRF52_ENABLE_SWO
  if (dbg_connected())
  {
    setupSWO();
  }
#endif

  nvram_init();
  clear_bss();
  enable_fault_exceptions();
  select_clocks();
  uwork_init();
  libc_init();

  main();
  if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)
    __BKPT(0);
  NVIC_SystemReset();
}

void
_xassert(const char *file, int lineno)
{
  __disable_irq();
  dbg_panic();
  printf("Assertion failed: file %s, line %d.\n", file, lineno);
  dbg_drain();

  if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)
    __BKPT(0);
  NVIC_SystemReset();
}

void uip_log(char *msg)
{
  printf("UIP: %s\r\n", msg);
}

/* TODO: Implement handlers */
void
NMI_Handler(void)
{
  __asm volatile (
    " ldr r0, =%[cdbg] \n"
    " ldr r0, [r0, %[dhcsr]]\n"
    " lsls r0, r0, #31\n"
    " bpl 3f           \n"
    " bkpt #0          \n"
   "3:                 \n"
   " b NVIC_SystemReset\n"
  :
  : [cdbg]        "X" (CoreDebug)
  , [dhcsr]       "J" (offsetof(CoreDebug_Type, DHCSR))
  );
}

__attribute__((naked)) void
HardFault_Handler(void)
{
  /*
    Thanks to Erich Styger.
    http://mcuoneclipse.com/2012/11/24/debugging-hard-faults-on-arm-cortex-m/
    The assembly code checks which stack we are using (MSP or PSP),
    and then loads the offending PC position on the stack into the register R1.
    So R1 will contain the code address where the problem happened:
  */
  __asm volatile (
    " movs r0, #4      \n"
    " movs r1, lr      \n"
    " tst r0, r1       \n"
    " beq 1f           \n"
    " mrs r0, psp      \n"
    " b 2f             \n"
  "1:                  \n"
    " mrs r0, msp      \n"
  "2:                  \n"
    " ldr r1, [r0,#24] \n"
    " ldr r0, =%[cdbg] \n"
    " ldr r0, [r0, %[dhcsr]]\n"
    " lsls r0, r0, #31\n"
    " bpl 3f           \n"
    " bkpt #0          \n"
   "3:                 \n"
   " b NVIC_SystemReset\n"
  :
  : [cdbg]        "X" (CoreDebug)
  , [dhcsr]       "J" (offsetof(CoreDebug_Type, DHCSR))
  );
}

__attribute__((naked)) void
UsageFault_Handler(void)
{
  /*
    Thanks to Erich Styger.
    http://mcuoneclipse.com/2012/11/24/debugging-hard-faults-on-arm-cortex-m/
    The assembly code checks which stack we are using (MSP or PSP),
    and then loads the offending PC position on the stack into the register R1.
    So R1 will contain the code address where the problem happened:
  */
  __asm volatile (
    " movs r0, #4      \n"
    " movs r1, lr      \n"
    " tst r0, r1       \n"
    " beq 1f           \n"
    " mrs r0, psp      \n"
    " b 2f             \n"
  "1:                  \n"
    " mrs r0, msp      \n"
  "2:                  \n"
    " ldr r1, [r0,#24] \n"
    " ldr r0, =%[cdbg] \n"
    " ldr r0, [r0, %[dhcsr]]\n"
    " lsls r0, r0, #31\n"
    " bpl 3f           \n"
    " bkpt #0          \n"
   "3:                 \n"
   " b NVIC_SystemReset\n"
  :
  : [cdbg]        "X" (CoreDebug)
  , [dhcsr]       "J" (offsetof(CoreDebug_Type, DHCSR))
  );
}

void
MemManage_Handler(void)
{
  __asm volatile (
    " ldr r0, =%[cdbg] \n"
    " ldr r0, [r0, %[dhcsr]]\n"
    " lsls r0, r0, #31\n"
    " bpl 3f           \n"
    " bkpt #0          \n"
   "3:                 \n"
   " b NVIC_SystemReset\n"
  :
  : [cdbg]        "X" (CoreDebug)
  , [dhcsr]       "J" (offsetof(CoreDebug_Type, DHCSR))
  );
}

void
BusFault_Handler(void)
{
  __asm volatile (
    " ldr r0, =%[cdbg] \n"
    " ldr r0, [r0, %[dhcsr]]\n"
    " lsls r0, r0, #31\n"
    " bpl 3f           \n"
    " bkpt #0          \n"
   "3:                 \n"
   " b NVIC_SystemReset\n"
  :
  : [cdbg]        "X" (CoreDebug)
  , [dhcsr]       "J" (offsetof(CoreDebug_Type, DHCSR))
  );
}