sc16is7x0.h

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#ifndef SC16IS7XX_H
#define SC16IS7XX_H
/**********************************************************************/
/*
 * Copyright (c) 2014, Jetro AS
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONRIBUTORS ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 * This file is part of the EVE platform.
 */

/**
 * \file
 * @brief Driver for SC16IS740/SC16IS750/SC16IS760 chip UART and GPIO.
 *
 * @author SE, Jetro AS
 */ /******************************************************************/

#include <dev/uart.h>
#include <dev/gpio-ext.h>
#include <dev/spi.h>

/** \defgroup sc16 SC16IS7x0 chip driver
 *  \ingroup extdrv
 */

/** \defgroup uart_sc16 SC16IS7x0 UART driver
 *  \ingroup sc16
 *  \ingroup uart
 *  \{
 */

/***********************************************************************
 * Global defines
 ***********************************************************************/

/**
 * SC16 register addresses
 */
#define SC16_REG_RHR       0x00 //!< RHR/THR Receive Holding / Transmit Holding
#define SC16_REG_THR       0x00 //!< RHR/THR Receive Holding / Transmit Holding
#define SC16_REG_IER       0x01 //!< IER Interrupt Enable
#define SC16_REG_FCR       0x02 //!< FCR/IIR FIFO Control
#define SC16_REG_IIR       0x02 //!< FCR/IIR FIFO Control
#define SC16_REG_LCR       0x03 //!< LCR Line Control
#define SC16_REG_MCR       0x04 //!< MCR Modem Control
#define SC16_REG_LSR       0x05 //!< LSR Line Status
#define SC16_REG_MSR       0x06 //!< MSR/TCR Modem Status / Transmission Control (TCR is selected by EFR[4] = 1 and MCR[2] = 1)
#define SC16_REG_TCR       0x06 //!< MSR/TCR Modem Status / Transmission Control (TCR is selected by EFR[4] = 1 and MCR[2] = 1)
#define SC16_REG_TLR       0x07 //!< TLR Trigger Level (can only be written to when EFR[4] = 1 and MCR[2] = 1)
#define SC16_REG_TXLVL     0x08 //!< TXLVL Transmitter FIFO Level
#define SC16_REG_RXLVL     0x09 //!< RXLVL Receiver FIFO Level
#define SC16_REG_IODIR     0x0A //!< SC16_REG_DIRECTION
#define SC16_REG_IOSTATE   0x0B //!< SC16_REG_PORT     
#define SC16_REG_IOINT     0x0C //!< SC16_REG_INT_MASK
#define SC16_REG_IOCTRL    0x0E //!< SC16_REG_CONTROL
#define SC16_REG_EFCR      0x0F //!< EFCR Extra Features Control

/**
 * SC16 special register set, accessible only when LCR[7] = 1 and not 0xBF
 */
#define SC16_REG_DLL   0x00 //!< Division register low
#define SC16_REG_DLH   0x01 //!< Division register high

/**
 * SC16 enhanced register set, accessible only when LCR = 0xBF.
 */
#define SC16_REG_EFR        0x02 //!< EFR Enhanced Features Register - Set LCR to 0xBF to access it!
#define SC16_REG_XON1       0x04 //!< XON1 char
#define SC16_REG_XON2       0x05 //!< XON2 char
#define SC16_REG_XOFF1      0x06 //!< XOFF1 char
#define SC16_REG_XOFF2      0x07 //!< XOFF2 char

/**
 * IER Interrupt Enable Register bits
 */
#define SC16_BIT_IER_CTS     (1 << 7) //!< CTS interrupt enable
#define SC16_BIT_IER_RTS     (1 << 6) //!< RTS interrupt enable
#define SC16_BIT_IER_XOFF    (1 << 5) //!< Xoff interrupt enable
#define SC16_BIT_IER_SLEEP   (1 << 4) //!< enable Sleep mode enable
#define SC16_BIT_IER_MODEM   (1 << 3) //!< Modem Status Interrupt enable
#define SC16_BIT_IER_LINE    (1 << 2) //!< Receive Line Status interrupt enable
#define SC16_BIT_IER_TX      (1 << 1) //!< Transmit Holding Register interrupt enable
#define SC16_BIT_IER_RX      (1 << 0) //!< Receive Holding Register interrupt enable

/**
 * FCR FIFO Control Register bits 
 */
#define SC16_SHIFT_FCR_RX_TRIGGER       (6) //!< 2 bits defining RX trigger. Sets the trigger level for the RX FIFO
#define SC16_SHIFT_FCR_TX_TRIGGER       (4) //!< 2 bits defining TX trigger. Sets the trigger level for the TX FIFO.
#define SC16_BIT_FCR_RESET_TX      (1 << 2) //!< reset TX FIFO
#define SC16_BIT_FCR_RESET_RX      (1 << 1) //!< reset RX FIFO
#define SC16_BIT_FCR_FIFO_ENABLE   (1 << 0) //!< FIFO enable

/**
 * IIR register bits
 */
#define SC16_BIT_IIR_NONE         0x01     //!< No interrupts pending
#define SC16_BIT_IIR_THR          0x02     //!< THR interrupt
#define SC16_BIT_IIR_RHR          0x04     //!< RHR interrupt
#define SC16_BIT_IIR_RXE          0x06     //!< Receive Line Status error
#define SC16_BIT_IIR_RTO          0x0C     //!< Receiver time-out interrupt
#define SC16_BIT_IIR_IO           0x30     //!< Input pin change of state


/**
 * LCR Line Control Register bits
 */
#define SC16_BIT_LCR_DIVISOR_LATCH (1 << 7) //!< divisor latch enable
#define SC16_BIT_LCR_BREAK         (1 << 6) //!< Break control bit. When enabled, the break control bit causes a break condition to be transmitted 
#define SC16_BIT_LCR_PARITY_FORCED (1 << 5) //!< forced parity (inverted SC16_BIT_LCR_PARITY_EVEN)
#define SC16_BIT_LCR_PARITY_EVEN   (1 << 4) //!< parity type (odd/even)
#define SC16_BIT_LCR_PARITY_ENABLE (1 << 3) //!< parity enable 
#define SC16_BIT_LCR_STOPS         (1 << 2) //!< Number of stop bits
#define SC16_SHIFT_LCR_WORD_LENGTH      (0)  //!< 2 bits for selection of Word length 

/**
 * MCR Modem Control Register bits
 */
#define SC16_BIT_MCR_CLOCK_DIVISOR (1 << 7) //!< 0 = clock/1, 1 = clock/4
#define SC16_BIT_MCR_IRDA          (1 << 6) //!< 0 = normal UART mode, 1 = IrDA mode
#define SC16_BIT_MCR_XON_ANY       (1 << 5) //!< 1 = enable Xon Any function
#define SC16_BIT_MCR_LOOPBACK      (1 << 4) //!<  1 = enable local Loopback mode
#define SC16_BIT_MCR_TCR_ENABLE    (1 << 2) //!< enable the TCR and TLR register.
#define SC16_BIT_MCR_FORCE_RTS     (1 << 1) //!< 0 = force RTS to inactive (HIGH), 1 = force RTS to active (LOW).
#define SC16_BIT_MCR_FORCE_DTR     (1 << 0) //!< Force DTR. Only in modem mode!

/**
 * LSR Line Status Register bits
 */
#define SC16_BIT_LSR_FIFO_ERR      (1 << 7) //!< FIFO data error
#define SC16_BIT_LSR_TX_EMPTY      (1 << 6) //!< THR and TSR empty. This bit is the Transmit Empty indicator
#define SC16_BIT_LSR_THR_EMPTY     (1 << 5) //!< Transmit Holding Register Empty indicator
#define SC16_BIT_LSR_BREAK         (1 << 4) //!< A break condition occurred
#define SC16_BIT_LSR_FRAME_ERR     (1 << 3) //!< received data did not have a valid stop bit
#define SC16_BIT_LSR_PARITY_ERR    (1 << 2) //!< parity error in data being read from RX FIFO
#define SC16_BIT_LSR_OVERRUN       (1 << 1) //!< overrun error has occurred
#define SC16_BIT_LSR_RX_READY      (1 << 0) //!< there is at least one character in the RX FIFO

/**
 * TCR Transmission Control Register bits
 */
#define SC16_SHIFT_TCR_FIFO_RESUME      (4)  //!< 4 bits for RX FIFO level to resume transmission
#define SC16_SHIFT_TCR_FIFO_HALT        (0)  //!< 4 bits for RX FIFO level to halt transmission

/**
 * TLR Trigger Level Register bits
 */
#define SC16_SHIFT_TLR_RX_FIFO          (4)  //!< 4 bits for RX FIFO levels (4 to 60) to generate interrupt
#define SC16_SHIFT_TLR_TX_FIFO          (0)  //!< 4 bits for TX FIFO levels (4 to 60) to generate interrupt

/**
 * EFCR Extra Features Control Register bits
 */
#define SC16_BIT_EFCR_IRDA_MODE    (1 << 7) //!< IrDA mode
#define SC16_BIT_EFCR_RTS_INVERT   (1 << 5) //!< invert RTS signal in RS-485 mode
#define SC16_BIT_EFCR_RTS_AUTO     (1 << 4) //!< enable the transmitter to control the RTS pin
#define SC16_BIT_EFCR_TX_OFF       (1 << 2) //!< Disable transmitter
#define SC16_BIT_EFCR_RX_OFF       (1 << 1) //!< Disable receiver
#define SC16_BIT_EFCR_9BIT         (1 << 0) //!< Enable 9-bit or Multidrop mode (RS-485)

/**
 * EFR Enhanced Features Control Register bits
 */
#define SC16_BIT_EFR_CTS_ON        (1 << 7) //!< CTS flow control enable
#define SC16_BIT_EFR_RTS_ON        (1 << 6) //!< RTS flow control enable
#define SC16_BIT_EFR_SPECIAL_CHAR  (1 << 5) //!< Special character detect (in XOFF2 register)
#define SC16_BIT_EFR_ENHANCED_ON   (1 << 4) //!< Enhanced functions enable
#define SC16_SHIFT_EFR_FLOW_CTRL        (0) //!< 4 bits for flow control selection
#define SC16_EFR_ACCESS                0xBF //!< This value should be written to LCR register in order to access EFR

/**
 * IOCtrl I/O Control Register bits
 */
#define SC16_BIT_IOCTRL_SRESET      (1 << 3) //!< Software reset. A write to bit will reset the device. Once the device is reset this bit is automatically set to ‘0’
#define SC16_BIT_IOCTRL_GPIO_ON     (1 << 1) //!< This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR pins. 0 = I/O pins, 1 = modem
#define SC16_BIT_IOCTRL_IOLATCH     (1 << 0) //!< Enable/disable inputs latching (keep value caused interrupt in IOState until it is read)

#define SC16_CHANNEL_A               0  //!< Select channel A UART on sc16is750, the only setting on sc16is740
#define SC16_CHANNEL_B               1  //!< Select channel B UART on sc16is750

#define SC16_FIFO_SIZE 64  //!< Tx/Rx FIFO length

/** UART Rx result */
typedef enum
{
  SC16RX_OK,
  SC16RX_TO,
  SC16RX_ERR,
} sc16_rxresult_t;

/** UART FIFO on/off settings */
enum uart_fifo_t
{
  UART_FIFO_OFF = 0,
  UART_FIFO_ON = 1,
};

/** UART FIFO trigger settings
 *  1) RX threshold level to halt transmission in auto flow control mode
 *  2) RX threshold level to resume transmission in auto flow control mode
 *  3) Generating interrupt if TX has the settled number of free bytes
 *  4) Generating interrupt if RX contains the settled number of bytes received
 */
enum uart_fifo_trigger_t
{
  UART_FIFO_4  = 1,
  UART_FIFO_8  = 2,
  UART_FIFO_12 = 3,
  UART_FIFO_16 = 4,
  UART_FIFO_20 = 5,
  UART_FIFO_24 = 6,
  UART_FIFO_28 = 7,
  UART_FIFO_32 = 8,
  UART_FIFO_36 = 9,
  UART_FIFO_40 = 10,
  UART_FIFO_44 = 11,
  UART_FIFO_48 = 12,
  UART_FIFO_52 = 13,
  UART_FIFO_56 = 14,
  UART_FIFO_60 = 15
};

/** UART 9-bit (multidrop) mode control */
enum rs485_wordlength_t
{
  RS485_WORDLENGTH_8 = 0,
  RS485_WORDLENGTH_9 = 1,
};

/** SC16 UART Tx/Rx state */
enum sc16_uart_status_t
{
  UART_STATUS_READY = 0,
  UART_STATUS_BUSY,
  UART_STATUS_BUSY_NOINT,
};

/** SC16 register read/write/set statemachine operation */
typedef enum
{
  SC16_SM_IDLE,
  SC16_SM_READREG,
  SC16_SM_WRITEREG,
  SC16_SM_RX,
  SC16_SM_TX,
  SC16_SM_SETREG,
} sc16_regmashine_oper_t;

/** SC16 register read/write/set statemachine state */
typedef enum
{
  SC16_REGMACHINE_IDLE = 0,
  SC16_REGMACHINE_START,
  SC16_REGMACHINE_ADDRESS,
  SC16_REGMACHINE_RX,
  SC16_REGMACHINE_TX,
  SC16_REGMACHINE_DONE,
} sc16_regmashine_state_t;

/** SC16 Tx handler statemachine state */
typedef enum
{
  SC16_TX_START = 0,
  SC16_TX_INT_ON,
  SC16_TX_WAIT_FIFO,
  SC16_TX_FIFO_LVL,
  SC16_TX_WRITE,
  SC16_TX_LOOP,
  SC16_TX_INT_OFF,
  SC16_TX_READ_LINE_STATUS,
  SC16_TX_FIFO_LVL_2,
  SC16_TX_FINISH,
} sc16_txmachine_state_t;

/** SC16 Tx handler statemachine state */
typedef enum
{
  SC16_RX_START = 0,
  SC16_RX_INT_ON,
  SC16_RX_SWITCH_ON,
  SC16_RX_LOOP_START,
  SC16_RX_FIFO_LVL,
  SC16_RX_READ,
  SC16_RX_LOOP_END,
  SC16_RX_INT_OFF,
  SC16_RX_SWITCH_OFF,
  SC16_RX_FINISH,
} sc16_rxmachine_state_t;

/** SC16 interrupt handler statemachine state */
typedef enum
{
  SC16_INT_START = 0,
  SC16_INT_READ_IIR,
  SC16_INT_SERVE,
} sc16_intmachine_state_t;

/** Descriptor for scheduled work of SC16 register statemachine */
struct sc16_reg_workitem_t
{
  struct work_t CbWork;
  uint8_t  Reg;       // Sc16 register address to read or write !ready! (shifted, with channel)
  uint8_t  Val;       // Sc16 register value to write or read to
  uint8_t  Mask;      // register bitmap for SET operation
  uint8_t* DataPtr;   // buffer for read / write operation
  uint16_t DataLen;   // length of buffer for read / write operation
  uint8_t  Buffer[2]; // SPI operational buffer
  sc16_regmashine_oper_t Operation;
};

/**
 * UART driver run-time state
 */
struct sc16_uart_state_t
{
  const struct uart_t* Uart;                 //!< Pointer to the parent structure
  uint8_t TxStatus;                          //!< Holds the current operative Tx status
  uint8_t RxStatus;                          //!< Holds the current operative Rx status
  uint8_t OverflowCounter;                   //!< Holds the position in FIFO of an overflow error
  sc16_rxresult_t RxResult : 8;              //!< Last Rx result (OK, interbyte timeout / line error)
  enum uart_rx_status_t RxError : 8;         //!< Rx result returned to the application
  sc16_txmachine_state_t TxStateMachine : 8; //!< Tx statemachine state
  struct sc16_reg_workitem_t TxRegWorkItem;  //!< Descriptior of Tx request to register statemachine
  struct uwork_t TxUwork;                    //!< uwork used by Tx on waiting for Tx end (empty FIFO)
  sc16_rxmachine_state_t RxStateMachine : 8; //!< Rx statemachine state
  struct sc16_reg_workitem_t RxRegWorkItem;  //!< Descriptior of Rx request to register statemachine
  struct sc16_reg_workitem_t RtsRegWorkItem; //!< Descriptior of SetRts request to register statemachine
  struct sc16_reg_workitem_t BrkRegWorkItem; //!< Descriptior of SendBreak request to register statemachine
};

/**
 * sc16_uart_t structure holds SPI instance and SC16 settings to be used
 */
struct sc16_uart_t
{
  struct sc16_uart_state_t*  State;    //!< Address of struct with RAM variables used by the uart driver
  const struct sc16_chip_t*   Chip;    //!< Address of SC16 chip descriptor
  uint32_t FifoRxTrigger       : 4;    //!< Generating interrupt if RX contains the settled number of bytes received, SC16 Trigger Level Register (TLR)
  uint32_t FifoTxTrigger       : 4;    //!< Generating interrupt if TX has the settled number of free bytes, SC16 Trigger Level Register (TLR)
  uint32_t FifoRxWatermarkLow  : 4;    //!< RX threshold level to resume transmission in auto flow control mode, SC16 Transmission Control Register (TCR)
  uint32_t FifoRxWatermarkHigh : 4;    //!< RX threshold level to halt transmission in auto flow control mode, SC16 Transmission Control Register (TCR)
  uint32_t RS485WordLength     : 1;    //!< Normal 8-bit or RS-485 multidrop 9-bit, SC16 Extra Features Control Register (EFCR)
  uint32_t RS485RtsAuto        : 1;    //!< RTS controlled by SC16 in RS485 mode, SC16 Extra Features Control Register (EFCR)
  uint32_t RS485RtsInverse     : 1;    //!< Inverse RTS (active 0) in RS485 mode, SC16 Extra Features Control Register (EFCR)
  uint32_t Channel             : 1;    //!< Select one of two UARTs on sc16is752 - SC16_CHANNEL_A or SC16_CHANNEL_B; should always be SC16_CHANNEL_A for sc16is750
};

/**
 * gpio_ext_sc16_t structure holds SC16 GPIO settings
 */
struct gpio_ext_sc16_t
{
  const struct sc16_chip_t* Chip;    //!< Pointer to SC16 chip settings
};

struct sc16_chip_state_t
{
  const struct sc16_chip_t* Chip;                     //!< SC16 chip settings
  sc16_intmachine_state_t InterruptStateMachine : 8;  //!< IRQ handler statemachine state
  uint8_t Iir[2];                                     //!< Last read IIR register from Uart0 and Uart1
  struct sc16_reg_workitem_t IntRegWorkItem;          //!< Descriptior of IRQ handler request to register statemachine
  struct dlist_t PendingRegWorks;                     //!< List of Register r/w works waiting
  struct work_t RegWork;                              //!< Work to be called when current Reg r/w completed
  sc16_regmashine_state_t RegState : 8;               //!< Register r/w statemachine state
  struct sc16_reg_workitem_t GpioRegWorkItem;         //!< Descriptior of GPIO request to register statemachine
  struct work_t IoWork;                               //!< work used by GPIO interrupt handler
  uint8_t InInterrupt : 1;                            //!< Flag: Inside interrupt handler, IRQ disabled
};

/**
 * sc16_chip_t structure holds SC16 chip settings common for both UARTS and GPIO
 */
struct sc16_chip_t
{
  struct sc16_chip_state_t* State;     //!< SC16 variables
  const struct spi_t* Spi;             //!< Pointer to the SPI interface instance
  struct spi_cs_t SpiCs;               //!< SPI CS settings
  uint32_t SpiBaudrate;                //!< SPI speed
  uint32_t Xtal;                       //!< SC16 quartz frequency
  uint8_t IrqPin;                      //!< HW IRQ pin number
  const struct uart_t* Uart[2];        //!< 2 SC16 Uarts
};

/**
 * Pointer to UartSc16Func structure uses to initialize the array of UART
 * virtual functions .Func in struct uart_t UART descriptor.
 */
extern const struct uart_api_t UartSc16Func;

/******************************************************************************
 * @name Functions called from application programs
 * @{
 *****************************************************************************/
 /** @name Internally synchronous functions
  *  @{ */
void Sc16Init(const struct sc16_chip_t* Chip);
void UartSc16Init(const struct uart_t *Uart);
void UartSc16Disable(const struct uart_t *Uart);
bool UartSc16IsBusyTx(const struct uart_t *Uart);
void UartSc16ResetFifo(const struct uart_t* Uart, bool Tx, bool Rx);
void UartSc16SetBaudrate(const struct uart_t *Uart);
void UartSc16SetRxTimeouts(const struct uart_t *Uart, uint32_t RxStartTimeoutUs, uint32_t RxStopTimeoutUs);
  /// @}
  /** @name Internally asynchronous functions
   *  @{ */
void UartSc16CancelTx(const struct uart_t *Uart);
void UartSc16StartBasicTx(const struct uart_t *Uart, uint8_t *DataSrc, uint16_t DataSize, uart_tx_callback_t Callback, void *CallbackData);
void UartSc16StartBasicRx(const struct uart_t *Uart, uint8_t *DataDest, uint16_t DataSize, uart_rx_callback_t Callback, void *CallbackData);
void UartSc16StartPingPongTx(const struct uart_t *Uart, uint8_t *PrimDataSrc, uint16_t PrimDataSize, uint8_t *AltDataSrc, uint16_t AltDataSize, uart_tx_callback_t Callback, void *CallbackData);
void UartSc16StartPingPongRx(const struct uart_t *Uart, uint8_t *PrimDataSrc, uint16_t PrimDataSize, uint8_t *AltDataSrc, uint16_t AltDataSize,uart_rx_callback_t Callback, void *CallbackData);
void UartSc16RefreshPingPongTx(const struct uart_t *Uart, uint8_t *DataSrc, uint16_t DataSize, bool Stop);
void UartSc16RefreshPingPongRx(const struct uart_t *Uart, uint8_t *DataDest, uint16_t DataSize, bool Stop);
void UartSc16CancelRx(const struct uart_t *Uart);
bool UartSc16IsBusyRx(const struct uart_t *Uart);
void UartSc16SendBreak(const struct uart_t *Uart, uart_break_callback_t Callback, void *CallbackData);
void UartSc16SetRts(const struct uart_t *Uart, bool Active);
void UartSc16InterruptHandler(struct work_t* Work);
  /// @}
/// @}

/** \} uart_sc16 */

/** \defgroup gpio_sc16 SC16IS7x0 GPIO driver
 *  \ingroup gpio_ext
 *  \ingroup sc16
 *  \{
 */

/**
 * Pointer to GpioSc16Func structure uses to initialize the array of GPIO
 * virtual functions .Func in struct ext_gpio_t GPIO descriptor.
 */
extern const struct gpio_ext_api_t GpioSc16Func;

/**
 *  @brief Synchronous function writes SC16 register asynchronously and waits
 *         for the end of the operation. Uses internally by inline functions.
 */
void Sc16OutPort(const struct gpio_ext_t *GpioExt, uint8_t Address, uint16_t Data);

/**
 *  @brief Synchronous function reads SC16 register asynchronously and waits
 *         for the end of the operation. Uses internally by inline functions.
 */
uint16_t Sc16InPort(const struct gpio_ext_t *GpioExt, uint8_t Address);

/**
 * @brief Initialize GPIO expander
 *
 * @param GpioExt  Parameters for the IO port expander to be used
 */
static inline void GpioExtInitSc16(const struct gpio_ext_t *GpioExt)
{
  // nothing to do
}

/**
 * @brief De-initialize IO expander
 *
 * @param GpioExt  Parameters for the IO port expander to be used
 */
static inline void GpioExtDisableSc16(const struct gpio_ext_t *GpioExt)
{
  // nothing to do
}

/**
 * @brief Read 8-bits data from GPIO port.
 *
 * @param GpioExt  Parameters for the IO port expander to be used
 * @return         Data read
 */
static inline uint16_t GpioExtInPortSc16(const struct gpio_ext_t *GpioExt)
{
  return Sc16InPort(GpioExt, SC16_REG_IOSTATE);
}

/**
 * @brief Write 8-bits data to GPIO port.
 *
 * @param GpioExt  Parameters for the IO port expander to be used
 * @param Data     Data to be written to IO expander ports
 */
static inline void GpioExtOutPortSc16(const struct gpio_ext_t *GpioExt, uint16_t Data)
{
  Sc16OutPort(GpioExt, SC16_REG_IOSTATE, Data);
}

/**
 * @brief Set pins direction to GPIO port.
 *
 * @param GpioExt     Parameters for the IO port expander to be used
 * @param Direction   New direction to be settled: 0 - input, 1 - output
 */
static inline void GpioExtSetDirectionSc16(const struct gpio_ext_t* GpioExt,
                                           uint16_t Direction)
{
  Sc16OutPort(GpioExt, SC16_REG_IODIR, Direction);
}

/**
 * @brief Select pullup or pulldown for GPIO port.
 *
 * @param GpioExt     Parameters for the IO port expander to be used
 * @param PullSelect  0 - pulldown, 1 - pullup
 */
static inline void GpioExtSetPullSelectSc16(const struct gpio_ext_t* GpioExt,
                                            uint16_t PullSelect)
{
  // Not supported by SC16: always pullup
}

/**
 * @brief Enable pullup/pulldown to GPIO port.
 *
 * @param GpioExt     Parameters for the IO port expander to be used
 * @param PullEnable  0 - disable, 1 - enable
 */
static inline void GpioExtSetPullEnableSc16(const struct gpio_ext_t* GpioExt,
                                            uint16_t PullEnable)
{
  // Not supported by SC16: always pullup
}

/**
 * @brief Enable/disable interrupts on input GPIO pins.
 *
 * @param GpioExt   Parameters for the IO port expander to be used
 * @param Mask      Each bit represents a pin #0-7, 1 enables interrupt.
 */
static inline void GpioExtSetInterruptsSc16(const struct gpio_ext_t *GpioExt, uint16_t Mask)
{
  Sc16OutPort(GpioExt, SC16_REG_IOINT, Mask);
}

/**
 * @brief Enable/disable latching values on input GPIO pins after interrupt
 *        until they are read.
 *
 * @param GpioExt   Parameters for the IO port expander to be used
 * @param Mask      Each bit represents a pin #0-7, 1 enables latching.
 */
static inline void GpioExtSetLatchSc16(const struct gpio_ext_t *GpioExt, uint16_t Mask)
{
  uint8_t Ctrl = Sc16InPort(GpioExt, SC16_REG_IOCTRL);
  if (Mask)
    Ctrl |= SC16_BIT_IOCTRL_IOLATCH;
  else
    Ctrl &= ~SC16_BIT_IOCTRL_IOLATCH;
  Sc16OutPort(GpioExt, SC16_REG_IOCTRL, Ctrl);
}

/**
 * @brief Set drive level for output pins.
 *
 * @param GpioExt   Parameters for the IO port expander to be used.
 * @param Values    Array represents drive for pins #1-7 in percents.
 */
static inline void GpioExtSetDriveSc16(const struct gpio_ext_t *GpioExt, uint8_t Values[])
{
  // Not supported by SC16
}

/** @} gpio_sc16 */

#endif // SC16IS7XX_H